paul@148 | 1 | = VGA Output Example (CPU-Driven Transfers) = |
paul@148 | 2 | |
paul@149 | 3 | This example demonstrates the generation of an analogue [[VGA Signal Output| |
paul@149 | 4 | VGA]] signal from a PIC32 microcontroller using general output pins. Instead |
paul@149 | 5 | of using DMA, which was the focus of the VGAPIC32 project and is a central |
paul@149 | 6 | feature of the approaches demonstrated by other examples ([[../vga|vga]], |
paul@148 | 7 | [[../vga-dual|vga-dual]], [[../vga-pmp|vga-pmp]], [[../vga-timer|vga-timer]]), |
paul@148 | 8 | here the CPU is given the task of transferring pixel data to the output pins. |
paul@148 | 9 | |
paul@148 | 10 | Instead of a timer interrupt condition initiating DMA transfers, the interrupt |
paul@148 | 11 | is handled and a routine invoked to issue the necessary load and store |
paul@148 | 12 | instructions in a loop. Otherwise, the use of the timer to generate sync |
paul@148 | 13 | pulses is as in the other examples and the general display state machine is |
paul@148 | 14 | largely the same. |
paul@148 | 15 | |
paul@148 | 16 | The resulting picture is more pleasing than that produced by most of the DMA |
paul@148 | 17 | examples in that the display pixels have consistent widths. Moreover, the |
paul@148 | 18 | pixels are also narrower than those produced by the [[../vga-timer|vga-timer]] |
paul@148 | 19 | example. It is possible to generate a display with something approaching 200 |
paul@148 | 20 | pixels horizontally, with 160 pixels being demonstrated. |
paul@148 | 21 | |
paul@148 | 22 | However, the CPU now spends a lot of time occupied in an interrupt request |
paul@148 | 23 | handler generating pixels. This seems less elegant than using DMA, but in |
paul@148 | 24 | practice, the CPU may be effectively stalled where DMA transfers dominate |
paul@148 | 25 | access to the RAM. Even if, in such situations, the CPU may be able to access |
paul@148 | 26 | flash memory to load instructions, programs typically end up accessing RAM at |
paul@148 | 27 | some point, and this would effectively limit the concurrency within the |
paul@148 | 28 | system. Certainly, this approach seems to result in slower programs than the |
paul@148 | 29 | plain DMA-based approach. |
paul@148 | 30 | |
paul@148 | 31 | One potential advantage of this approach is in the flexibility that might be |
paul@148 | 32 | achieved by manipulating the pixel data. With DMA, data is transferred as it |
paul@148 | 33 | is found and is generally not transformed (although there are some features in |
paul@148 | 34 | the PIC32 DMA controller for certain kinds of data), whereas we might envisage |
paul@148 | 35 | supporting display modes employing fewer bits for the output signal, reducing |
paul@148 | 36 | the number of colours but also the size of the framebuffer. |
paul@148 | 37 | |
paul@148 | 38 | == Hardware Details == |
paul@148 | 39 | |
paul@148 | 40 | The pin usage of this solution is documented below. |
paul@148 | 41 | |
paul@148 | 42 | === PIC32MX270F256B-50I/SP Pin Assignments === |
paul@148 | 43 | |
paul@148 | 44 | {{{ |
paul@148 | 45 | MCLR# 1 \/ 28 |
paul@148 | 46 | HSYNC/OC1/RA0 2 27 |
paul@148 | 47 | VSYNC/OC2/RA1 3 26 RB15/U1TX |
paul@148 | 48 | D0/RB0 4 25 RB14 |
paul@148 | 49 | D1/RB1 5 24 RB13/U1RX |
paul@148 | 50 | D2/RB2 6 23 |
paul@148 | 51 | D3/RB3 7 22 RB11/PGEC2 |
paul@148 | 52 | 8 21 RB10/PGEC3 |
paul@148 | 53 | RA2 9 20 |
paul@148 | 54 | RA3 10 19 |
paul@148 | 55 | D4/RB4 11 18 RB9 |
paul@148 | 56 | 12 17 RB8 |
paul@148 | 57 | 13 16 RB7/D7 |
paul@148 | 58 | D5/RB5 14 15 |
paul@148 | 59 | }}} |
paul@148 | 60 | |
paul@148 | 61 | Note that RB6 is not available on pin 15 on this device (it is needed for VBUS |
paul@148 | 62 | unlike the MX170 variant). |
paul@148 | 63 | |
paul@148 | 64 | === UART Connections === |
paul@148 | 65 | |
paul@148 | 66 | UART1 is exposed by the RB13 and RB15 pins. |
paul@148 | 67 | |
paul@148 | 68 | === Data Signal Routing === |
paul@148 | 69 | |
paul@148 | 70 | For one bit of intensity, two bits per colour channel: |
paul@148 | 71 | |
paul@148 | 72 | {{{ |
paul@148 | 73 | D7 -> 2200R -> I |
paul@148 | 74 | |
paul@148 | 75 | I -> diode -> R |
paul@148 | 76 | I -> diode -> G |
paul@148 | 77 | I -> diode -> B |
paul@148 | 78 | |
paul@148 | 79 | D6 (not connected) |
paul@148 | 80 | |
paul@148 | 81 | D5 -> 470R -> R |
paul@148 | 82 | D4 -> 1000R -> R |
paul@148 | 83 | D3 -> 470R -> G |
paul@148 | 84 | D2 -> 1000R -> G |
paul@148 | 85 | D1 -> 470R -> B |
paul@148 | 86 | D0 -> 1000R -> B |
paul@148 | 87 | |
paul@148 | 88 | HSYNC -> HS |
paul@148 | 89 | VSYNC -> VS |
paul@148 | 90 | }}} |