1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/intcond.S Tue Oct 16 23:26:17 2018 +0200
1.3 @@ -0,0 +1,95 @@
1.4 +/*
1.5 + * PIC32 microcontroller initialisation code.
1.6 + *
1.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software: you can redistribute it and/or modify
1.10 + * it under the terms of the GNU General Public License as published by
1.11 + * the Free Software Foundation, either version 3 of the License, or
1.12 + * (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 + */
1.22 +
1.23 +#include "mips.h"
1.24 +#include "pic32.h"
1.25 +
1.26 +/* Disable JTAG functionality on pins. */
1.27 +
1.28 +.section .devcfg0, "a"
1.29 +.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
1.30 +
1.31 +/*
1.32 +Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.33 +divided by 2, and FRCDIV+PLL selected.
1.34 +
1.35 +The watchdog timer (FWDTEN) is also disabled.
1.36 +
1.37 +The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.38 +RPB4.
1.39 +*/
1.40 +
1.41 +.section .devcfg1, "a"
1.42 +.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.43 + DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.44 +
1.45 +/*
1.46 +Set the FRC oscillator PLL function with an input division of 4, an output
1.47 +division of 2, a multiplication of 24, yielding a multiplication of 3.
1.48 +
1.49 +The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
1.50 +*/
1.51 +
1.52 +.section .devcfg2, "a"
1.53 +.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.54 + DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
1.55 + DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
1.56 +
1.57 +/* The start routine is placed at the boot location. */
1.58 +
1.59 +.section .boot, "a"
1.60 +
1.61 +.globl _start
1.62 +.extern main
1.63 +
1.64 +_start:
1.65 + /* Enable caching. */
1.66 +
1.67 + mfc0 $v1, CP0_CONFIG
1.68 + li $t8, ~CONFIG_K0
1.69 + and $v1, $v1, $t8
1.70 + ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
1.71 + mtc0 $v1, CP0_CONFIG
1.72 + nop
1.73 +
1.74 + /* Get the RAM size. */
1.75 +
1.76 + la $v1, BMXDRMSZ
1.77 + lw $t0, 0($v1)
1.78 +
1.79 + /* Initialise the stack pointer. */
1.80 +
1.81 + li $v1, KSEG0_BASE
1.82 + addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */
1.83 +
1.84 + /* Initialise the globals pointer. */
1.85 +
1.86 + lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
1.87 + ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
1.88 +
1.89 + /*
1.90 + Jump to the main program. Since the boot code is separate from the
1.91 + other code, the address cannot be obtained via the GOT.
1.92 + ("relocation truncated to fit: R_MIPS_PC16 against `main'")
1.93 + */
1.94 +
1.95 + lui $t9, %hi(main)
1.96 + ori $t9, $t9, %lo(main)
1.97 + jr $t9
1.98 + nop