1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/include/pic32.h Mon Oct 22 21:44:02 2018 +0200
1.3 @@ -0,0 +1,382 @@
1.4 +/*
1.5 + * PIC32 peripheral descriptions.
1.6 + *
1.7 + * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 + *
1.9 + * This program is free software: you can redistribute it and/or modify
1.10 + * it under the terms of the GNU General Public License as published by
1.11 + * the Free Software Foundation, either version 3 of the License, or
1.12 + * (at your option) any later version.
1.13 + *
1.14 + * This program is distributed in the hope that it will be useful,
1.15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 + * GNU General Public License for more details.
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License
1.20 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 + */
1.22 +
1.23 +#ifndef __PIC32_H__
1.24 +#define __PIC32_H__
1.25 +
1.26 +/* Peripheral addresses.
1.27 + * See...
1.28 + * TABLE 4-1: SFR MEMORYMAP
1.29 + * TABLE 11-3: PORTA REGISTER MAP
1.30 + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.31 + */
1.32 +
1.33 +#define OSCCON 0xBF80F000
1.34 +#define REFOCON 0xBF80F020
1.35 +#define REFOTRIM 0xBF80F030
1.36 +#define CFGCON 0xBF80F200
1.37 +#define SYSKEY 0xBF80F230
1.38 +
1.39 +#define INT2R 0xBF80FA08
1.40 +#define U1RXR 0xBF80FA50
1.41 +
1.42 +#define RPA0R 0xBF80FB00
1.43 +#define RPA1R 0xBF80FB04
1.44 +#define RPA2R 0xBF80FB08
1.45 +#define RPA3R 0xBF80FB0C
1.46 +#define RPA4R 0xBF80FB10
1.47 +#define RPB0R 0xBF80FB2C
1.48 +#define RPB1R 0xBF80FB30
1.49 +#define RPB2R 0xBF80FB34
1.50 +#define RPB3R 0xBF80FB38
1.51 +#define RPB4R 0xBF80FB3C
1.52 +#define RPB5R 0xBF80FB40
1.53 +#define RPB10R 0xBF80FB54
1.54 +#define RPB15R 0xBF80FB68
1.55 +
1.56 +#define INTCON 0xBF881000
1.57 +#define IFS0 0xBF881030
1.58 +#define IFS1 0xBF881040
1.59 +#define IEC0 0xBF881060
1.60 +#define IEC1 0xBF881070
1.61 +#define IPC0 0xBF881090
1.62 +#define IPC1 0xBF8810A0
1.63 +#define IPC2 0xBF8810B0
1.64 +#define IPC3 0xBF8810C0
1.65 +#define IPC4 0xBF8810D0
1.66 +#define IPC5 0xBF8810E0
1.67 +#define IPC6 0xBF8810F0
1.68 +#define IPC7 0xBF881100
1.69 +#define IPC8 0xBF881110
1.70 +#define IPC9 0xBF881120
1.71 +#define IPC10 0xBF881130
1.72 +
1.73 +#define BMXCON 0xBF882000
1.74 +#define BMXDKPBA 0xBF882010
1.75 +#define BMXDUDBA 0xBF882020
1.76 +#define BMXDUPBA 0xBF882030
1.77 +#define BMXDRMSZ 0xBF882040
1.78 +
1.79 +#define ANSELA 0xBF886000
1.80 +#define TRISA 0xBF886010
1.81 +#define PORTA 0xBF886020
1.82 +#define LATA 0xBF886030
1.83 +#define ODCA 0xBF886040
1.84 +#define ANSELB 0xBF886100
1.85 +#define TRISB 0xBF886110
1.86 +#define PORTB 0xBF886120
1.87 +#define LATB 0xBF886130
1.88 +#define ODCB 0xBF886140
1.89 +
1.90 +/* DEVCFG conveniences. */
1.91 +
1.92 +#define DEVCFG1_UNUSED 0xff7fcbd8 /* exclude FWDTWINSZ, WINDIS, WDTPS, FCKSM, POSCMOD, IESO */
1.93 +
1.94 +#define DEVCFG1_FWDTEN_OFF (0 << 23)
1.95 +#define DEVCFG1_FWDTEN_ON (1 << 23)
1.96 +
1.97 +#define DEVCFG1_FPBDIV_1 (0b00 << 12)
1.98 +#define DEVCFG1_FPBDIV_2 (0b01 << 12)
1.99 +#define DEVCFG1_FPBDIV_4 (0b10 << 12)
1.100 +#define DEVCFG1_FPBDIV_8 (0b11 << 12)
1.101 +
1.102 +#define DEVCFG1_OSCIOFNC_ON (0 << 10)
1.103 +#define DEVCFG1_OSCIOFNC_OFF (1 << 10)
1.104 +
1.105 +#define DEVCFG1_FSOSCEN_OFF (0 << 5)
1.106 +#define DEVCFG1_FSOSCEN_ON (1 << 5)
1.107 +
1.108 +#define DEVCFG1_FNOSC_FRC (0b000)
1.109 +#define DEVCFG1_FNOSC_FRCDIV_PLL (0b001)
1.110 +#define DEVCFG1_FNOSC_FRCDIV (0b111)
1.111 +
1.112 +#define DEVCFG2_UNUSED 0xfff8ff88 /* exclude UPLLEN, UPLLIDIV */
1.113 +
1.114 +#define DEVCFG2_FPLLODIV_1 (0b000 << 16)
1.115 +#define DEVCFG2_FPLLODIV_2 (0b001 << 16)
1.116 +#define DEVCFG2_FPLLODIV_4 (0b010 << 16)
1.117 +#define DEVCFG2_FPLLODIV_8 (0b011 << 16)
1.118 +#define DEVCFG2_FPLLODIV_16 (0b100 << 16)
1.119 +#define DEVCFG2_FPLLODIV_32 (0b101 << 16)
1.120 +#define DEVCFG2_FPLLODIV_64 (0b110 << 16)
1.121 +#define DEVCFG2_FPLLODIV_128 (0b111 << 16)
1.122 +
1.123 +#define DEVCFG2_FPLLMUL_15 (0b000 << 4)
1.124 +#define DEVCFG2_FPLLMUL_16 (0b001 << 4)
1.125 +#define DEVCFG2_FPLLMUL_17 (0b010 << 4)
1.126 +#define DEVCFG2_FPLLMUL_18 (0b011 << 4)
1.127 +#define DEVCFG2_FPLLMUL_19 (0b100 << 4)
1.128 +#define DEVCFG2_FPLLMUL_20 (0b101 << 4)
1.129 +#define DEVCFG2_FPLLMUL_21 (0b110 << 4)
1.130 +#define DEVCFG2_FPLLMUL_24 (0b111 << 4)
1.131 +
1.132 +#define DEVCFG2_FPLLIDIV_1 (0b000)
1.133 +#define DEVCFG2_FPLLIDIV_2 (0b001)
1.134 +#define DEVCFG2_FPLLIDIV_3 (0b010)
1.135 +#define DEVCFG2_FPLLIDIV_4 (0b011)
1.136 +#define DEVCFG2_FPLLIDIV_5 (0b100)
1.137 +#define DEVCFG2_FPLLIDIV_6 (0b101)
1.138 +#define DEVCFG2_FPLLIDIV_10 (0b110)
1.139 +#define DEVCFG2_FPLLIDIV_12 (0b111)
1.140 +
1.141 +/* DMA conveniences. */
1.142 +
1.143 +#define DMACON 0xBF883000
1.144 +#define DCH0CON 0xBF883060
1.145 +#define DCH1CON 0xBF883120
1.146 +#define DCH2CON 0xBF8831E0
1.147 +#define DCH3CON 0xBF8832A0
1.148 +
1.149 +#define DCHMIN 0
1.150 +#define DCHMAX 3
1.151 +#define DCHBASE DCH0CON
1.152 +#define DCHSTEP (DCH1CON - DCH0CON)
1.153 +
1.154 +#define DCHxCON 0x00
1.155 +#define DCHxECON 0x10
1.156 +#define DCHxINT 0x20
1.157 +#define DCHxSSA 0x30
1.158 +#define DCHxDSA 0x40
1.159 +#define DCHxSSIZ 0x50
1.160 +#define DCHxDSIZ 0x60
1.161 +#define DCHxSPTR 0x70
1.162 +#define DCHxDPTR 0x80
1.163 +#define DCHxCSIZ 0x90
1.164 +#define DCHxCPTR 0xA0
1.165 +#define DCHxDAT 0xB0
1.166 +
1.167 +#define DMAIEC IEC1
1.168 +
1.169 +#define DCHxIE 1
1.170 +
1.171 +#define DMAIFS IFS1
1.172 +
1.173 +#define DCHxIF 1
1.174 +
1.175 +#define DMAINTBASE 28
1.176 +
1.177 +#define DMAIPC IPC10
1.178 +#define DCHIPCBASE 0
1.179 +#define DCHIPCSTEP 8
1.180 +
1.181 +/* External interrupt conveniences. */
1.182 +
1.183 +#define INTMIN 0
1.184 +#define INTMAX 4
1.185 +
1.186 +#define INTIEC IEC0
1.187 +
1.188 +#define INTxIE 1
1.189 +
1.190 +#define INTIFS IFS0
1.191 +
1.192 +#define INTxIF 1
1.193 +
1.194 +#define INTINTBASE 3
1.195 +#define INTINTSTEP 5
1.196 +
1.197 +#define INT0IPC IPC0
1.198 +#define INT1IPC IPC1
1.199 +#define INT2IPC IPC2
1.200 +#define INT3IPC IPC3
1.201 +#define INT4IPC IPC4
1.202 +#define INTIPCBASE 24
1.203 +
1.204 +/* Output compare conveniences. */
1.205 +
1.206 +#define OC1CON 0xBF803000
1.207 +#define OC2CON 0xBF803200
1.208 +#define OC3CON 0xBF803400
1.209 +#define OC4CON 0xBF803600
1.210 +#define OC5CON 0xBF803800
1.211 +
1.212 +#define OCMIN 1
1.213 +#define OCMAX 5
1.214 +#define OCBASE OC1CON
1.215 +#define OCSTEP (OC2CON - OC1CON)
1.216 +
1.217 +#define OCxCON 0x00
1.218 +#define OCxR 0x10
1.219 +#define OCxRS 0x20
1.220 +
1.221 +#define OCIEC IEC0
1.222 +
1.223 +#define OCxIE 1
1.224 +
1.225 +#define OCIFS IFS0
1.226 +
1.227 +#define OCxIF 1
1.228 +
1.229 +#define OCINTBASE 7
1.230 +#define OCINTSTEP 5
1.231 +
1.232 +#define OC1IPC IPC1
1.233 +#define OC2IPC IPC2
1.234 +#define OC3IPC IPC3
1.235 +#define OC4IPC IPC4
1.236 +#define OC5IPC IPC5
1.237 +#define OCIPCBASE 16
1.238 +
1.239 +/* Parallel mode conveniences. */
1.240 +
1.241 +#define PMCON 0xBF807000
1.242 +
1.243 +#define PMxCON 0x00
1.244 +#define PMxMODE 0x10
1.245 +#define PMxADDR 0x20
1.246 +#define PMxDOUT 0x30
1.247 +#define PMxDIN 0x40
1.248 +#define PMxAEN 0x50
1.249 +#define PMxSTAT 0x60
1.250 +
1.251 +#define PMMIN 0
1.252 +#define PMMAX 0
1.253 +#define PMBASE PMCON
1.254 +#define PMSTEP 0
1.255 +
1.256 +#define PMIEC IEC1
1.257 +
1.258 +#define PMxIE 1
1.259 +#define PMxEIE 2
1.260 +
1.261 +#define PMIFS IFS1
1.262 +
1.263 +#define PMxIF 1
1.264 +#define PMxEIF 2
1.265 +
1.266 +#define PMINTBASE 16
1.267 +#define PMINTSTEP 0
1.268 +
1.269 +#define PMIPC IPC8
1.270 +#define PMIPCBASE 24
1.271 +
1.272 +/* Timer conveniences. */
1.273 +
1.274 +#define T1CON 0xBF800600
1.275 +#define T2CON 0xBF800800
1.276 +#define T3CON 0xBF800A00
1.277 +#define T4CON 0xBF800C00
1.278 +#define T5CON 0xBF800E00
1.279 +
1.280 +#define TIMERMIN 1
1.281 +#define TIMERMAX 5
1.282 +#define TIMERBASE T1CON
1.283 +#define TIMERSTEP (T2CON - T1CON)
1.284 +
1.285 +#define TxCON 0x00
1.286 +#define TMRx 0x10
1.287 +#define PRx 0x20
1.288 +
1.289 +#define TIMERIEC IEC0
1.290 +
1.291 +#define TxIE 1
1.292 +
1.293 +#define TIMERIFS IEC0
1.294 +
1.295 +#define TxIF 1
1.296 +
1.297 +#define TIMERINTBASE 4
1.298 +#define TIMERINTSTEP 5
1.299 +
1.300 +#define TIMER1IPC IPC1
1.301 +#define TIMER2IPC IPC2
1.302 +#define TIMER3IPC IPC3
1.303 +#define TIMER4IPC IPC4
1.304 +#define TIMER5IPC IPC5
1.305 +#define TIMERIPCBASE 0
1.306 +
1.307 +/* UART conveniences. */
1.308 +
1.309 +#define U1MODE 0xBF806000
1.310 +#define U2MODE 0xBF806200
1.311 +
1.312 +#define UARTMIN 1
1.313 +#define UARTMAX 2
1.314 +#define UARTBASE U1MODE
1.315 +#define UARTSTEP (U2MODE - U1MODE)
1.316 +
1.317 +#define UxMODE 0x00
1.318 +#define UxSTA 0x10
1.319 +#define UxTXREG 0x20
1.320 +#define UxRXREG 0x30
1.321 +#define UxBRG 0x40
1.322 +
1.323 +#define UARTIEC IEC1
1.324 +
1.325 +#define UxEIE 1
1.326 +#define UxRIE 2
1.327 +#define UxTIE 4
1.328 +
1.329 +#define UARTIFS IFS1
1.330 +
1.331 +#define UxEIF 1
1.332 +#define UxRIF 2
1.333 +#define UxTIF 4
1.334 +
1.335 +#define UARTINTBASE 7
1.336 +#define UARTINTSTEP 14
1.337 +
1.338 +#define UART1IPC IPC8
1.339 +#define UART1IPCBASE 0
1.340 +#define UART2IPC IPC9
1.341 +#define UART2IPCBASE 8
1.342 +
1.343 +/* Interrupt numbers.
1.344 + * See...
1.345 + * TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION
1.346 + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.347 + */
1.348 +
1.349 +#define DMA0 60
1.350 +#define DMA1 61
1.351 +#define DMA2 62
1.352 +#define DMA3 63
1.353 +#define INT0 3
1.354 +#define INT1 8
1.355 +#define INT2 13
1.356 +#define INT3 18
1.357 +#define INT4 23
1.358 +#define OC1 7
1.359 +#define OC2 12
1.360 +#define OC3 17
1.361 +#define OC4 22
1.362 +#define OC5 27
1.363 +#define PMP 48
1.364 +#define PMPE 49
1.365 +#define T1 4
1.366 +#define T2 9
1.367 +#define T3 14
1.368 +#define T4 19
1.369 +#define T5 24
1.370 +#define U1RX 40
1.371 +#define U1TX 41
1.372 +#define U2RX 54
1.373 +#define U2TX 55
1.374 +
1.375 +/* Address modifiers.
1.376 + * See...
1.377 + * 11.2 CLR, SET and INV Registers
1.378 + * PIC32MX1XX/2XX 28/36/44-pin Family Data Sheet
1.379 + */
1.380 +
1.381 +#define CLR 0x4
1.382 +#define SET 0x8
1.383 +#define INV 0xC
1.384 +
1.385 +#endif /* __PIC32_H__ */