1.1 --- a/pic32.h Sat Oct 20 23:51:55 2018 +0200
1.2 +++ b/pic32.h Sun Oct 21 01:43:38 2018 +0200
1.3 @@ -41,6 +41,7 @@
1.4 #define CFGCON 0xBF80F200
1.5 #define SYSKEY 0xBF80F230
1.6
1.7 +#define INT2R 0xBF80FA08
1.8 #define U1RXR 0xBF80FA50
1.9
1.10 #define RPA0R 0xBF80FB00
1.11 @@ -62,6 +63,7 @@
1.12 #define IFS1 0xBF881040
1.13 #define IEC0 0xBF881060
1.14 #define IEC1 0xBF881070
1.15 +#define IPC0 0xBF881090
1.16 #define IPC1 0xBF8810A0
1.17 #define IPC2 0xBF8810B0
1.18 #define IPC3 0xBF8810C0
1.19 @@ -130,6 +132,29 @@
1.20 #define DCHIPCBASE 0
1.21 #define DCHIPCSTEP 8
1.22
1.23 +/* External interrupt conveniences. */
1.24 +
1.25 +#define INTMIN 0
1.26 +#define INTMAX 4
1.27 +
1.28 +#define INTIEC IEC0
1.29 +
1.30 +#define INTxIE 1
1.31 +
1.32 +#define INTIFS IFS0
1.33 +
1.34 +#define INTxIF 1
1.35 +
1.36 +#define INTINTBASE 3
1.37 +#define INTINTSTEP 5
1.38 +
1.39 +#define INT0IPC IPC0
1.40 +#define INT1IPC IPC1
1.41 +#define INT2IPC IPC2
1.42 +#define INT3IPC IPC3
1.43 +#define INT4IPC IPC4
1.44 +#define INTIPCBASE 24
1.45 +
1.46 /* Output compare conveniences. */
1.47
1.48 #define OC1CON 0xBF803000
1.49 @@ -246,6 +271,11 @@
1.50 #define DMA1 61
1.51 #define DMA2 62
1.52 #define DMA3 63
1.53 +#define INT0 3
1.54 +#define INT1 8
1.55 +#define INT2 13
1.56 +#define INT3 18
1.57 +#define INT4 23
1.58 #define OC1 7
1.59 #define OC2 12
1.60 #define OC3 17