1.1 --- a/intcond.S Wed Oct 17 17:53:08 2018 +0200
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,98 +0,0 @@
1.4 -/*
1.5 - * PIC32 microcontroller initialisation code.
1.6 - *
1.7 - * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk>
1.8 - *
1.9 - * This program is free software: you can redistribute it and/or modify
1.10 - * it under the terms of the GNU General Public License as published by
1.11 - * the Free Software Foundation, either version 3 of the License, or
1.12 - * (at your option) any later version.
1.13 - *
1.14 - * This program is distributed in the hope that it will be useful,
1.15 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1.16 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1.17 - * GNU General Public License for more details.
1.18 - *
1.19 - * You should have received a copy of the GNU General Public License
1.20 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1.21 - */
1.22 -
1.23 -#include "mips.h"
1.24 -#include "pic32.h"
1.25 -
1.26 -/* Disable JTAG functionality on pins. */
1.27 -
1.28 -.section .devcfg0, "a"
1.29 -.word 0xfffffffb /* DEVCFG0<2> = JTAGEN = 0 */
1.30 -
1.31 -/*
1.32 -Set the oscillator to be the FRC oscillator with PLL, with peripheral clock
1.33 -divided by 2, and FRCDIV+PLL selected.
1.34 -
1.35 -The watchdog timer (FWDTEN) is also disabled.
1.36 -
1.37 -The secondary oscillator pin (FSOSCEN) is disabled to avoid pin conflicts with
1.38 -RPB4.
1.39 -*/
1.40 -
1.41 -.section .devcfg1, "a"
1.42 -.word 0xff7fdfd9 /* DEVCFG1<23> = FWDTEN = 0; DEVCFG1<13:12> = FPBDIV<1:0> = 1;
1.43 - DEVCFG1<5> = FSOSCEN = 0; DEVCFG1<2:0> = FNOSC<2:0> = 001 */
1.44 -
1.45 -/*
1.46 -Set the FRC oscillator PLL function with an input division of 4, an output
1.47 -division of 2, a multiplication of 24, yielding a multiplication of 3.
1.48 -
1.49 -The FRC is apparently at 16MHz and this produces a system clock of 48MHz.
1.50 -
1.51 -The peripheral clock frequency (FPB) will be 24MHz given the above DEVCFG1
1.52 -settings.
1.53 -*/
1.54 -
1.55 -.section .devcfg2, "a"
1.56 -.word 0xfff9fffb /* DEVCFG2<18:16> = FPLLODIV<2:0> = 001;
1.57 - DEVCFG2<6:4> = FPLLMUL<2:0> = 111;
1.58 - DEVCFG2<2:0> = FPLLIDIV<2:0> = 011 */
1.59 -
1.60 -/* The start routine is placed at the boot location. */
1.61 -
1.62 -.section .boot, "a"
1.63 -
1.64 -.globl _start
1.65 -.extern main
1.66 -
1.67 -_start:
1.68 - /* Enable caching. */
1.69 -
1.70 - mfc0 $v1, CP0_CONFIG
1.71 - li $t8, ~CONFIG_K0
1.72 - and $v1, $v1, $t8
1.73 - ori $v1, $v1, CONFIG_K0_CACHABLE_NONCOHERENT
1.74 - mtc0 $v1, CP0_CONFIG
1.75 - nop
1.76 -
1.77 - /* Get the RAM size. */
1.78 -
1.79 - la $v1, BMXDRMSZ
1.80 - lw $t0, 0($v1)
1.81 -
1.82 - /* Initialise the stack pointer. */
1.83 -
1.84 - li $v1, KSEG0_BASE
1.85 - addu $sp, $t0, $v1 /* sp = KSEG0_BASE + RAM size */
1.86 -
1.87 - /* Initialise the globals pointer. */
1.88 -
1.89 - lui $gp, %hi(_GLOBAL_OFFSET_TABLE_)
1.90 - ori $gp, $gp, %lo(_GLOBAL_OFFSET_TABLE_)
1.91 -
1.92 - /*
1.93 - Jump to the main program. Since the boot code is separate from the
1.94 - other code, the address cannot be obtained via the GOT.
1.95 - ("relocation truncated to fit: R_MIPS_PC16 against `main'")
1.96 - */
1.97 -
1.98 - lui $t9, %hi(main)
1.99 - ori $t9, $t9, %lo(main)
1.100 - jr $t9
1.101 - nop