1.1 --- a/pic32_c.h Thu Oct 18 17:58:45 2018 +0200
1.2 +++ b/pic32_c.h Thu Oct 18 18:24:48 2018 +0200
1.3 @@ -9,24 +9,62 @@
1.4
1.5 /* Access. */
1.6
1.7 -#define REG(mem) *((volatile uint32_t *) (mem))
1.8 +#define REG(mem) *((volatile uint32_t *) (mem))
1.9
1.10 /* Bit clearing, setting and inverting. */
1.11
1.12 -#define CLR_REG(mem, val) (REG(mem + CLR) = val)
1.13 -#define SET_REG(mem, val) (REG(mem + SET) = val)
1.14 -#define INV_REG(mem, val) (REG(mem + INV) = val)
1.15 +static inline void CLR_REG(uint32_t mem, uint32_t val)
1.16 +{
1.17 + REG(mem + CLR) = val;
1.18 +}
1.19 +
1.20 +static inline void SET_REG(uint32_t mem, uint32_t val)
1.21 +{
1.22 + REG(mem + SET) = val;
1.23 +}
1.24 +
1.25 +static inline void INV_REG(uint32_t mem, uint32_t val)
1.26 +{
1.27 + REG(mem + INV) = val;
1.28 +}
1.29
1.30 /* Address translation. */
1.31
1.32 -#define PHYSICAL(addr) (((uint32_t) addr) - KSEG0_BASE)
1.33 -#define HW_PHYSICAL(addr) (((uint32_t) addr) - KSEG1_BASE)
1.34 +static inline uint32_t PHYSICAL(uint32_t addr)
1.35 +{
1.36 + return ((uint32_t) addr) - KSEG0_BASE;
1.37 +}
1.38 +
1.39 +static inline uint32_t HW_PHYSICAL(uint32_t addr)
1.40 +{
1.41 + return ((uint32_t) addr) - KSEG1_BASE;
1.42 +}
1.43
1.44 /* Register collection access. */
1.45
1.46 -#define DMA_REG(channel, reg) (DCHBASE + reg + (channel - DCHMIN) * DCHSTEP)
1.47 -#define TIMER_REG(channel, reg) (TIMERBASE + reg + (channel - TIMERMIN) * TIMERSTEP)
1.48 -#define UART_REG(channel, reg) (UARTBASE + reg + (channel - UARTMIN) * UARTSTEP)
1.49 +static inline uint32_t DMA_REG(int channel, uint32_t reg)
1.50 +{
1.51 + return DCHBASE + reg + (channel - DCHMIN) * DCHSTEP;
1.52 +}
1.53 +
1.54 +static inline uint32_t TIMER_REG(int channel, uint32_t reg)
1.55 +{
1.56 + return TIMERBASE + reg + (channel - TIMERMIN) * TIMERSTEP;
1.57 +}
1.58 +
1.59 +static inline uint32_t UART_REG(int channel, uint32_t reg)
1.60 +{
1.61 + return UARTBASE + reg + (channel - UARTMIN) * UARTSTEP;
1.62 +}
1.63 +
1.64 +/* Convenience types. */
1.65 +
1.66 +enum dma_chain
1.67 +{
1.68 + dma_chain_none,
1.69 + dma_chain_next,
1.70 + dma_chain_previous,
1.71 +};
1.72
1.73 #endif /* __PIC32_C_H__ */
1.74