1 /* 2 * Generate a VGA signal using a PIC32 microcontroller. 3 * 4 * Copyright (C) 2017, 2018 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 3 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "pic32_c.h" 22 #include "init.h" 23 #include "debug.h" 24 25 /* Specific functionality. */ 26 27 #include "main.h" 28 #include "devconfig.h" 29 #include "vga.h" 30 #include "display.h" 31 32 33 34 /* Display state. */ 35 36 static void (*state_handler)(void); 37 static uint32_t line; 38 39 /* Pointers to pixel lines. */ 40 41 static uint8_t *linedata, *linedatalimit, *screenstart; 42 43 /* Pixel data. */ 44 45 static const uint8_t zerodata[ZERO_LENGTH] = {0}; 46 static uint8_t framebuffer[SCREEN_SIZE]; 47 48 49 50 /* Blink an attached LED with delays implemented using a loop. */ 51 52 static void blink(uint32_t delay, uint32_t port, uint32_t pins) 53 { 54 uint32_t counter; 55 56 /* Clear outputs (LED). */ 57 58 CLR_REG(port, pins); 59 60 while (1) 61 { 62 counter = delay; 63 64 while (counter--) __asm__(""); /* retain loop */ 65 66 /* Invert outputs (LED). */ 67 68 INV_REG(port, pins); 69 } 70 } 71 72 73 74 /* Main program. */ 75 76 void main(void) 77 { 78 line = 0; 79 state_handler = vbp_active; 80 test_linedata(framebuffer); 81 82 /* Initialise the current display line pointer and display limit. */ 83 84 linedatalimit = framebuffer + SCREEN_SIZE; 85 screenstart = framebuffer; 86 87 init_memory(); 88 init_pins(); 89 init_outputs(); 90 91 unlock_config(); 92 config_oc(); 93 config_uart(); 94 lock_config(); 95 96 init_dma(); 97 98 /* Initiate DMA on the Timer2 interrupt transferring line data to the first 99 byte of PORTB. Do not enable the channel for initiation until the visible 100 region is about to start. */ 101 102 dma_init(0, 3); 103 dma_set_auto_enable(0, 1); 104 dma_set_interrupt(0, T2, 1); 105 dma_set_transfer(0, PHYSICAL((uint32_t) screenstart), LINE_LENGTH, 106 HW_PHYSICAL(PORTB), 1, 107 TRANSFER_CELL_SIZE); 108 109 /* Enable DMA on the preceding channel's completion, with the timer event 110 initiating the transfer. */ 111 112 dma_init(1, 3); 113 dma_set_chaining(1, dma_chain_previous); 114 dma_set_interrupt(1, T2, 1); 115 dma_set_transfer(1, PHYSICAL((uint32_t) zerodata), ZERO_LENGTH, 116 HW_PHYSICAL(PORTB), 1, 117 ZERO_LENGTH); 118 dma_set_receive_events(1, 1); 119 120 /* Configure a timer for the horizontal sync. The timer has no prescaling 121 (0). */ 122 123 timer_init(2, 0, HFREQ_LIMIT); 124 timer_on(2); 125 126 /* Horizontal sync. */ 127 128 /* Configure output compare in dual compare (continuous output) mode using 129 Timer2 as time base. The interrupt condition drives the first DMA channel 130 and is handled to drive the display state machine. */ 131 132 oc_init(1, 0b101, 2); 133 oc_set_pulse(1, HSYNC_END); 134 oc_set_pulse_end(1, HSYNC_START); 135 oc_init_interrupt(1, 7, 3); 136 oc_on(1); 137 138 /* Vertical sync. */ 139 140 /* Configure output compare in single compare (output driven low) mode using 141 Timer2 as time base. The unit is enabled later. It is only really used to 142 achieve precisely-timed level transitions in hardware. */ 143 144 oc_init(2, 0b010, 2); 145 oc_set_pulse(2, 0); 146 147 uart_init(1, FPB, 115200); 148 uart_on(1); 149 150 interrupts_on(); 151 152 blink(3 << 24, PORTA, 1 << 3); 153 } 154 155 156 157 /* Exception and interrupt handlers. */ 158 159 void exception_handler(void) 160 { 161 blink(3 << 12, PORTA, 1 << 3); 162 } 163 164 void interrupt_handler(void) 165 { 166 uint32_t ifs; 167 168 /* Check for a OC1 interrupt condition. */ 169 170 ifs = REG(OCIFS) & OC_INT_FLAGS(1, OCxIF); 171 172 if (ifs) 173 { 174 line += 1; 175 state_handler(); 176 CLR_REG(OCIFS, ifs); 177 } 178 } 179 180 181 182 /* Vertical back porch region. */ 183 184 void vbp_active(void) 185 { 186 if (line < VISIBLE_START) 187 return; 188 189 /* Enter the visible region. */ 190 191 state_handler = visible_active; 192 193 /* Set the line address. */ 194 195 linedata = screenstart; 196 dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH); 197 198 /* Enable the channel for the next line. */ 199 200 dma_on(0); 201 } 202 203 /* Visible region. */ 204 205 void visible_active(void) 206 { 207 INV_REG(PORTA, 1 << 2); 208 209 if (line < VFP_START) 210 { 211 /* Update the line address and handle wraparound. */ 212 213 if (!(line % LINE_MULTIPLIER)) 214 { 215 linedata += LINE_LENGTH; 216 if (linedata >= linedatalimit) 217 linedata -= SCREEN_SIZE; 218 } 219 220 dma_set_source(0, PHYSICAL((uint32_t) linedata), LINE_LENGTH); 221 return; 222 } 223 224 /* End the visible region. */ 225 226 state_handler = vfp_active; 227 228 /* Disable the channel for the next line. */ 229 230 dma_off(0); 231 } 232 233 /* Vertical front porch region. */ 234 235 void vfp_active(void) 236 { 237 if (line < VSYNC_START) 238 return; 239 240 /* Enter the vertical sync region. */ 241 242 state_handler = vsync_active; 243 244 /* Bring vsync low (single compare, output driven low) when the next line 245 starts. */ 246 247 oc_init(2, 0b010, 2); 248 oc_on(2); 249 } 250 251 /* Vertical sync region. */ 252 253 void vsync_active(void) 254 { 255 if (line < VSYNC_END) 256 return; 257 258 /* Start again at the top of the display. */ 259 260 line = 0; 261 state_handler = vbp_active; 262 263 /* Bring vsync high (single compare, output driven high) when the next line 264 starts. */ 265 266 oc_init(2, 0b001, 2); 267 oc_on(2); 268 } 269 270 271 272 /* Peripheral pin configuration. */ 273 274 void config_oc(void) 275 { 276 /* Map OC1 to RPA0. */ 277 278 REG(RPA0R) = 0b0101; /* RPA0R<3:0> = 0101 (OC1) */ 279 280 /* Map OC2 to RPA1. */ 281 282 REG(RPA1R) = 0b0101; /* RPA1R<3:0> = 0101 (OC2) */ 283 } 284 285 void config_uart(void) 286 { 287 /* Map U1RX to RPB13. */ 288 289 REG(U1RXR) = 0b0011; /* U1RXR<3:0> = 0011 (RPB13) */ 290 291 /* Map U1TX to RPB15. */ 292 293 REG(RPB15R) = 0b0001; /* RPB15R<3:0> = 0001 (U1TX) */ 294 295 /* Set RPB13 to input. */ 296 297 SET_REG(TRISB, 1 << 13); 298 }