# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1540380081 -7200
# Node ID 4335ebcaa12234223678da2215926658c15f0f53
# Parent  7f7124c7c2974ddd2823a5014843a8cff83982a0
Adjusted the pixel channel priority to hopefully avoid ordering problems.
Adjusted the position of the pixel data on the display.

diff -r 7f7124c7c297 -r 4335ebcaa122 examples/vga-timer/main.c
--- a/examples/vga-timer/main.c	Wed Oct 24 13:03:22 2018 +0200
+++ b/examples/vga-timer/main.c	Wed Oct 24 13:21:21 2018 +0200
@@ -109,7 +109,7 @@
     /* Enable DMA on the zero channel's completion, with the Timer3
        interrupt condition initiating transfers. */
 
-    dma_init(0, 3);
+    dma_init(0, 2);
     dma_set_chaining(0, dma_chain_next);
     dma_set_interrupt(0, T3, 1);
     dma_set_transfer(0, PHYSICAL((uint32_t) display_config.screen_start),
@@ -120,7 +120,7 @@
     /* Enable DMA on the zero channel's completion, with the Timer3
        interrupt condition initiating transfers. */
 
-    dma_init(2, 3);
+    dma_init(2, 2);
     dma_set_chaining(2, dma_chain_previous);
     dma_set_interrupt(2, T3, 1);
     dma_set_transfer(2, PHYSICAL((uint32_t) display_config.screen_start +
diff -r 7f7124c7c297 -r 4335ebcaa122 examples/vga-timer/vga.h
--- a/examples/vga-timer/vga.h	Wed Oct 24 13:03:22 2018 +0200
+++ b/examples/vga-timer/vga.h	Wed Oct 24 13:21:21 2018 +0200
@@ -29,7 +29,7 @@
 /* 24MHz cycle measurements. */
 
 #define HFREQ_LIMIT             643
-#define HSYNC_START             504
+#define HSYNC_START             508
 #define HSYNC_LIMIT             40
 #define HSYNC_END               (HSYNC_START + HSYNC_LIMIT)