# HG changeset patch # User Paul Boddie # Date 1540387916 -7200 # Node ID 43cfde9693e2fa180306cc7a211352a580c57cd4 # Parent 4335ebcaa12234223678da2215926658c15f0f53 Moved horizontal/vertical sync configuration into a common library module. diff -r 4335ebcaa122 -r 43cfde9693e2 examples/vga-dual/main.c --- a/examples/vga-dual/main.c Wed Oct 24 13:21:21 2018 +0200 +++ b/examples/vga-dual/main.c Wed Oct 24 15:31:56 2018 +0200 @@ -118,32 +118,10 @@ ZERO_LENGTH); dma_set_receive_events(2, 1); - /* Configure a timer for the horizontal sync. The timer has no prescaling - (0). */ - - timer_init(2, 0, HFREQ_LIMIT); - timer_on(2); - - /* Horizontal sync. */ - - /* Configure output compare in dual compare (continuous output) mode using - Timer2 as time base. The interrupt condition drives the first DMA channel - and is handled to drive the display state machine. */ + /* Configure a timer and output compare units for horizontal and vertical + sync. */ - oc_init(1, 0b101, 2); - oc_set_pulse(1, HSYNC_END); - oc_set_pulse_end(1, HSYNC_START); - oc_init_interrupt(1, 7, 3); - oc_on(1); - - /* Vertical sync. */ - - /* Configure output compare in single compare (output driven low) mode using - Timer2 as time base. The unit is enabled later. It is only really used to - achieve precisely-timed level transitions in hardware. */ - - oc_init(2, 0b010, 2); - oc_set_pulse(2, 0); + vga_configure_sync(1, 2, 2); uart_init(1, FPB, 115200); uart_on(1); diff -r 4335ebcaa122 -r 43cfde9693e2 examples/vga-pmp/main.c --- a/examples/vga-pmp/main.c Wed Oct 24 13:21:21 2018 +0200 +++ b/examples/vga-pmp/main.c Wed Oct 24 15:31:56 2018 +0200 @@ -115,32 +115,10 @@ ZERO_LENGTH); dma_set_receive_events(1, 1); - /* Configure a timer for the horizontal sync. The timer has no prescaling - (0). */ - - timer_init(2, 0, HFREQ_LIMIT); - timer_on(2); - - /* Horizontal sync. */ - - /* Configure output compare in dual compare (continuous output) mode using - Timer2 as time base. The interrupt condition drives the first DMA channel - and is handled to drive the display state machine. */ + /* Configure a timer and output compare units for horizontal and vertical + sync. */ - oc_init(1, 0b101, 2); - oc_set_pulse(1, HSYNC_END); - oc_set_pulse_end(1, HSYNC_START); - oc_init_interrupt(1, 7, 3); - oc_on(1); - - /* Vertical sync. */ - - /* Configure output compare in single compare (output driven low) mode using - Timer2 as time base. The unit is enabled later. It is only really used to - achieve precisely-timed level transitions in hardware. */ - - oc_init(2, 0b010, 2); - oc_set_pulse(2, 0); + vga_configure_sync(1, 2, 2); uart_init(1, FPB, 115200); uart_on(1); diff -r 4335ebcaa122 -r 43cfde9693e2 examples/vga-timer/main.c --- a/examples/vga-timer/main.c Wed Oct 24 13:21:21 2018 +0200 +++ b/examples/vga-timer/main.c Wed Oct 24 15:31:56 2018 +0200 @@ -140,37 +140,15 @@ ZERO_LENGTH); dma_set_receive_events(3, 1); - /* Configure a timer for the horizontal sync. The timer has no prescaling - (0). */ - - timer_init(2, 0, HFREQ_LIMIT); - timer_on(2); - /* Configure a timer for line data transfers. */ timer_init(3, 0, 1); timer_on(3); - /* Horizontal sync. */ - - /* Configure output compare in dual compare (continuous output) mode using - Timer2 as time base. The interrupt condition drives the first DMA channel - and is handled to drive the display state machine. */ + /* Configure a timer and output compare units for horizontal and vertical + sync. */ - oc_init(1, 0b101, 2); - oc_set_pulse(1, HSYNC_END); - oc_set_pulse_end(1, HSYNC_START); - oc_init_interrupt(1, 7, 3); - oc_on(1); - - /* Vertical sync. */ - - /* Configure output compare in single compare (output driven low) mode using - Timer2 as time base. The unit is enabled later. It is only really used to - achieve precisely-timed level transitions in hardware. */ - - oc_init(2, 0b010, 2); - oc_set_pulse(2, 0); + vga_configure_sync(1, 2, 2); uart_init(1, FPB, 115200); uart_on(1); diff -r 4335ebcaa122 -r 43cfde9693e2 examples/vga/main.c --- a/examples/vga/main.c Wed Oct 24 13:21:21 2018 +0200 +++ b/examples/vga/main.c Wed Oct 24 15:31:56 2018 +0200 @@ -106,32 +106,10 @@ ZERO_LENGTH); dma_set_receive_events(1, 1); - /* Configure a timer for the horizontal sync. The timer has no prescaling - (0). */ - - timer_init(2, 0, HFREQ_LIMIT); - timer_on(2); - - /* Horizontal sync. */ - - /* Configure output compare in dual compare (continuous output) mode using - Timer2 as time base. The interrupt condition drives the first DMA channel - and is handled to drive the display state machine. */ + /* Configure a timer and output compare units for horizontal and vertical + sync. */ - oc_init(1, 0b101, 2); - oc_set_pulse(1, HSYNC_END); - oc_set_pulse_end(1, HSYNC_START); - oc_init_interrupt(1, 7, 3); - oc_on(1); - - /* Vertical sync. */ - - /* Configure output compare in single compare (output driven low) mode using - Timer2 as time base. The unit is enabled later. It is only really used to - achieve precisely-timed level transitions in hardware. */ - - oc_init(2, 0b010, 2); - oc_set_pulse(2, 0); + vga_configure_sync(1, 2, 2); uart_init(1, FPB, 115200); uart_on(1); diff -r 4335ebcaa122 -r 43cfde9693e2 include/display.h --- a/include/display.h Wed Oct 24 13:21:21 2018 +0200 +++ b/include/display.h Wed Oct 24 15:31:56 2018 +0200 @@ -46,6 +46,10 @@ int cell_size; + /* Display line positions. */ + + uint32_t hfreq_limit, hsync_start, hsync_end; + /* Display region scanline positions. */ uint32_t visible_start, vfp_start, vsync_start, vsync_end; diff -r 4335ebcaa122 -r 43cfde9693e2 include/display_config.h --- a/include/display_config.h Wed Oct 24 13:21:21 2018 +0200 +++ b/include/display_config.h Wed Oct 24 15:31:56 2018 +0200 @@ -1,5 +1,6 @@ /* - * Initialisation of application-specific display configuration. + * Initialisation of application-specific display configuration. This requires + * the prior definition of various display properties. * * Copyright (C) 2018 Paul Boddie * @@ -42,6 +43,9 @@ /* Define display region properties. */ + .hfreq_limit = HFREQ_LIMIT, + .hsync_start = HSYNC_START, + .hsync_end = HSYNC_END, .visible_start = VISIBLE_START, .vfp_start = VFP_START, .vsync_start = VSYNC_START, diff -r 4335ebcaa122 -r 43cfde9693e2 include/vga_display.h --- a/include/vga_display.h Wed Oct 24 13:21:21 2018 +0200 +++ b/include/vga_display.h Wed Oct 24 15:31:56 2018 +0200 @@ -68,6 +68,8 @@ void (*vsync_high)(), void (*vsync_low)()); +void vga_configure_sync(int hsync_unit, int vsync_unit, int timer); + /* Interrupt handlers. */ void vga_interrupt_handler(void); diff -r 4335ebcaa122 -r 43cfde9693e2 lib/vga_display.c --- a/lib/vga_display.c Wed Oct 24 13:21:21 2018 +0200 +++ b/lib/vga_display.c Wed Oct 24 15:31:56 2018 +0200 @@ -18,6 +18,7 @@ */ #include "pic32_c.h" +#include "init.h" #include "vga_display.h" @@ -58,6 +59,39 @@ vga_display.line = 0; } +/* Configure a timer and output compare units for horizontal and vertical + sync. */ + +void vga_configure_sync(int hsync_unit, int vsync_unit, int timer) +{ + /* Configure a timer for the horizontal sync. The timer has no prescaling + (0). */ + + timer_init(timer, 0, vga_display.display_config->hfreq_limit); + timer_on(timer); + + /* Horizontal sync. */ + + /* Configure output compare in dual compare (continuous output) mode using + the timer as time base. The interrupt condition drives the first DMA + channel and is handled to drive the display state machine. */ + + oc_init(hsync_unit, 0b101, timer); + oc_set_pulse(hsync_unit, vga_display.display_config->hsync_end); + oc_set_pulse_end(hsync_unit, vga_display.display_config->hsync_start); + oc_init_interrupt(hsync_unit, 7, 3); + oc_on(hsync_unit); + + /* Vertical sync. */ + + /* Configure output compare in single compare (output driven low) mode using + the timer as time base. The unit is enabled later. It is only really used + to achieve precisely-timed level transitions in hardware. */ + + oc_init(vsync_unit, 0b010, timer); + oc_set_pulse(vsync_unit, 0); +} + /* Interrupt handlers. */