1 /* 2 * I2C support for the X1600. 3 * 4 * Copyright (C) 2017, 2018, 2021, 2023 Paul Boddie <paul@boddie.org.uk> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 19 * Boston, MA 02110-1301, USA 20 */ 21 22 #include <l4/devices/i2c-x1600.h> 23 #include <l4/devices/hw_mmio_register_block.h> 24 25 #include <l4/sys/icu.h> 26 #include <l4/util/util.h> 27 #include <sys/time.h> 28 29 #include <stdio.h> 30 31 /* NOTE: This peripheral is very similar to the JZ4780 with the registers 32 renamed to I2C from SMB, with a few high speed registers added, and 33 with I2C_SDAHD appearing at a different location. */ 34 35 enum Regs 36 { 37 I2c_control = 0x000, // I2C_CON 38 I2c_target_address = 0x004, // I2C_TAR 39 I2c_slave_address = 0x008, // I2C_SAR 40 I2c_master_code = 0x00c, // I2C_HS_MADDR 41 I2c_data_command = 0x010, // I2C_DC 42 Std_high_count = 0x014, // I2C_SHCNT 43 Std_low_count = 0x018, // I2C_SLCNT 44 Fast_high_count = 0x01c, // I2C_FHCNT 45 Fast_low_count = 0x020, // I2C_FLCNT 46 High_high_count = 0x024, // I2C_HHCNT 47 High_low_count = 0x028, // I2C_HLCNT 48 Int_status = 0x02c, // I2C_INTST (read-only) 49 Int_mask = 0x030, // I2C_INTM 50 Int_raw_status = 0x034, // I2C_RINTST (read-only) 51 Rx_fifo_thold = 0x038, // I2C_RXTL 52 Tx_fifo_thold = 0x03c, // I2C_TXTL 53 Int_combined_clear = 0x040, // I2C_CINT (read-only) 54 Int_rx_uf_clear = 0x044, // I2C_CRXUF (read-only) 55 Int_rx_of_clear = 0x048, // I2C_CRXOF (read-only) 56 Int_tx_of_clear = 0x04c, // I2C_CTXOF (read-only) 57 Int_rd_req_clear = 0x050, // I2C_CRXREQ (read-only) 58 Int_tx_abort_clear = 0x054, // I2C_CTXABT (read-only) 59 Int_rx_done_clear = 0x058, // I2C_CRXDN (read-only) 60 Int_activity_clear = 0x05c, // I2C_CACT (read-only) 61 Int_stop_clear = 0x060, // I2C_CSTP (read-only) 62 Int_start_clear = 0x064, // I2C_CSTT (read-only) 63 Int_call_clear = 0x068, // I2C_CGC (read-only) 64 I2c_enable = 0x06c, // I2C_ENB 65 I2c_status = 0x070, // I2C_ST (read-only) 66 Tx_fifo_count = 0x074, // I2C_TXFLR (read-only) 67 Rx_fifo_count = 0x078, // I2C_RXFLR (read-only) 68 I2c_sda_hold_time = 0x07c, // I2C_SDAHD 69 Trans_abort_status = 0x080, // I2C_ABTSRC (read-only) 70 Slv_data_nack = 0x084, // I2CSDNACK 71 I2c_dma_ctrl = 0x088, // I2C_DMACR 72 I2c_trans_data_lvl = 0x08c, // I2C_DMATDLR 73 I2c_recv_data_lvl = 0x090, // I2C_DMARDLR 74 I2c_sda_setup_time = 0x094, // I2C_SDASU 75 I2c_ack_call = 0x098, // I2C_ACKGC 76 I2c_enable_status = 0x09c, // I2C_ENBST (read-only) 77 I2c_spike_suppress = 0x0a0, // I2C_FSPKLEN 78 79 I2c_block_offset = 0x1000 80 }; 81 82 enum I2c_control_bits : unsigned 83 { 84 I2c_disable_slave = 0x40, // SLVDIS (slave disabled) 85 I2c_enable_restart = 0x20, // RESTART 86 I2c_master_10bit = 0x10, // MATP (read-only) 87 I2c_slave_10bit = 0x08, // SATP 88 I2c_speed_mode_mask = 0x06, // SPEED 89 I2c_enable_master = 0x01, // MD (master enabled) 90 I2c_speed_bit = 1, // SPD 91 }; 92 93 enum I2c_speed_mode_values : unsigned 94 { 95 I2c_speed_standard = 1, 96 I2c_speed_fast = 2, 97 I2c_speed_high = 3, 98 }; 99 100 enum I2c_enable_bits : unsigned 101 { 102 I2c_enable_enabled = 0x01, // I2CEN 103 }; 104 105 enum I2c_status_bits : unsigned 106 { 107 I2c_status_master_act = 0x20, // MSTACT (master active) 108 I2c_status_rx_nempty = 0x08, // RFNE (read queue not empty) 109 I2c_status_tx_empty = 0x04, // TFE (write queue empty) 110 I2c_status_tx_nfull = 0x02, // TFNF (write queue not full) 111 I2c_status_active = 0x01, // ACT (device active as master or slave) 112 }; 113 114 enum I2c_target_bits : unsigned 115 { 116 I2c_target_master_10bit = 0x1000, 117 I2c_target_special = 0x0800, // SPECIAL: perform general call or start byte 118 I2c_target_start_byte = 0x0400, // Special: start byte (1) or general call (0) 119 I2c_target_10bits = 0x3ff, // Mask for 10-bit address 120 I2c_target_7bits = 0x7f, // Mask for 7-bit address 121 }; 122 123 enum I2c_hold_control_bits : unsigned 124 { 125 /* The hold enable flag has been removed since the JZ4780 and the hold time 126 field widened. */ 127 128 I2c_hold_mask = 0xffff, 129 }; 130 131 enum I2c_setup_control_bits : unsigned 132 { 133 I2c_setup_mask = 0x0ff, // SDASU 134 }; 135 136 enum I2c_command_bits : unsigned 137 { 138 I2c_command_restart = 0x400, // RESTART: explicit restart before next byte 139 I2c_command_stop = 0x200, // STOP: explicit stop after next byte 140 I2c_command_no_stop = 0x000, 141 I2c_command_read = 0x100, // CMD 142 I2c_command_write = 0x000, // CMD 143 }; 144 145 enum I2c_fifo_bits : unsigned 146 { 147 I2c_fifo_limit = 64, // RXTL, TXTL (256 noted in field description) 148 }; 149 150 enum Int_bits : unsigned 151 { 152 Int_call = 0x800, // IGC (general call received) 153 Int_start = 0x400, // ISTT (start/restart condition occurred) 154 Int_stop = 0x200, // ISTP (stop condition occurred) 155 Int_activity = 0x100, // IACT (bus activity interrupt) 156 Int_rx_done = 0x080, // RXDN (read from master device done) 157 Int_tx_abort = 0x040, // TXABT (transmit abort) 158 Int_rd_req = 0x020, // RDREQ (read request from master device) 159 Int_tx_empty = 0x010, // TXEMP (threshold reached or passed) 160 Int_tx_of = 0x008, // TXOF (overflow when writing to queue) 161 Int_rx_full = 0x004, // RXFL (threshold reached or exceeded) 162 Int_rx_of = 0x002, // RXOF (overflow from device) 163 Int_rx_uf = 0x001, // RXUF (underflow when reading from queue) 164 }; 165 166 167 168 // Initialise a channel. 169 170 I2c_x1600_channel::I2c_x1600_channel(l4_addr_t start, 171 Cpm_x1600_chip *cpm, 172 uint32_t frequency) 173 : _cpm(cpm), _frequency(frequency) 174 { 175 _regs = new Hw::Mmio_register_block<32>(start); 176 177 // NOTE: Previously located in set_target. 178 179 disable(); 180 set_frequency(); 181 enable(); 182 } 183 184 // Enable the channel. 185 186 void 187 I2c_x1600_channel::enable() 188 { 189 _regs[I2c_enable] = I2c_enable_enabled; 190 while (!(_regs[I2c_enable_status] & I2c_enable_enabled)); 191 } 192 193 // Disable the channel. 194 195 void 196 I2c_x1600_channel::disable() 197 { 198 _regs[I2c_enable] = 0; 199 while (_regs[I2c_enable_status] & I2c_enable_enabled); 200 } 201 202 // Return the configured frequency. 203 204 uint32_t 205 I2c_x1600_channel::get_frequency() 206 { 207 return _frequency; 208 } 209 210 // Set the frequency-related peripheral parameters. 211 212 void 213 I2c_x1600_channel::set_frequency() 214 { 215 // The APB clock (PCLK) is used to drive I2C transfers. Its value must be 216 // obtained from the CPM unit. It is known as I2C_DEV_CLK here and is scaled 217 // to kHz in order to keep the numbers easily representable, as is the bus 218 // frequency. 219 220 uint32_t i2c_dev_clk = _cpm->get_frequency(Clock_pclock) / 1000; 221 222 // Note that this is not I2C_DEV_CLK but the actual I2C bus frequency. 223 224 uint32_t i2c_clk = _frequency / 1000; 225 226 // Select the appropriate speed. 227 228 unsigned int speed = (i2c_clk <= 100) ? I2c_speed_standard 229 : (i2c_clk <= 400 ? I2c_speed_fast 230 : I2c_speed_high); 231 232 // NOTE: Permit broader configuration elsewhere. 233 234 _regs[I2c_control] = (speed << I2c_speed_bit) | 235 I2c_disable_slave | 236 I2c_enable_restart | 237 I2c_enable_master; 238 239 printf("I2c_control = %02x\n", (uint32_t) _regs[I2c_control]); 240 241 // According to the programming manual, if the PCLK period is T{I2C_DEV_CLK} 242 // then the I2C clock period is... 243 244 // T{SCL} = T{SCL_high} + T{SCL_low} 245 246 // Where... 247 248 // T{SCL_low} = T{I2C_DEV_CLK} * (#cycles for low signal) 249 // T{SCL_high} = T{I2C_DEV_CLK} * (#cycles for high signal) 250 251 // Since, with minimum periods being defined... 252 253 // T{SCL} >= T{min_SCL} 254 // T{SCL_low} >= T{min_SCL_low} 255 // T{SCL_high} >= T{min_SCL_high} 256 // T{min_SCL} = T{min_SCL_low} + T{min_SCL_high} 257 258 // Then the following applies... 259 260 // T{I2C_DEV_CLK} * (#cycles for low signal)) >= T{min_SCL_low} 261 // T{I2C_DEV_CLK} * (#cycles for high signal) >= T{min_SCL_high} 262 263 // To work with different clock speeds while maintaining the low-to-high 264 // ratios: 265 266 // T{min_SCL_low} = T{min_SCL} * T{min_SCL_low} / T{min_SCL} 267 // = T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) 268 269 // T{min_SCL_high} = T{min_SCL} * T{min_SCL_high} / T{min_SCL} 270 // = T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) 271 272 // Constraints are given with respect to the high and low count registers. 273 274 // #cycles for high signal = I2CxHCNT + 8 275 // #cycles for low signal = I2CxLCNT + 1 276 277 // From earlier, this yields... 278 279 // T{I2C_DEV_CLK} * (I2CxLCNT + 1) >= T{min_SCL_low} 280 // T{I2C_DEV_CLK} * (I2CxHCNT + 8) >= T{min_SCL_high} 281 282 // Rearranging... 283 284 // I2CxLCNT >= (T{min_SCL_low} / T{I2C_DEV_CLK}) - 1 285 // >= T{min_SCL_low} * I2C_DEV_CLK - 1 286 287 // I2CxHCNT >= (T{min_SCL_high} / T{I2C_DEV_CLK}) - 8 288 // >= T{min_SCL_high} * I2C_DEV_CLK - 8 289 290 // Introducing the definitions for the high and low periods... 291 292 // I2CxLCNT >= T{min_SCL} * (T{min_SCL_low} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 1 293 // >= (T{min_SCL_low} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 1 294 295 // I2CxHCNT >= T{min_SCL} * (T{min_SCL_high} / (T{min_SCL_low} + T{min_SCL_high})) * I2C_DEV_CLK - 8 296 // >= (T{min_SCL_high} / T{min_SCL}) * I2C_DEV_CLK / I2C_BUS_CLK - 8 297 298 uint32_t high_reg, low_reg; 299 uint32_t high_count, low_count; 300 int32_t hold_count; 301 uint32_t setup_count; 302 303 // Level hold times: 304 305 // Standard Fast High 306 // SCL low 4.7us 1.3us 0.5us 307 // SCL high 4.0us 0.6us 0.26us + 308 // SCL period 8.7us 1.9us 0.76us = 309 310 // See: UM10204 "I2C-bus specification and user manual" 311 // Table 10: t{LOW} and t{HIGH} 312 313 if (i2c_clk <= 100) // 100 kHz 314 { 315 low_count = (i2c_dev_clk * 47) / (i2c_clk * 87) - 1; 316 high_count = (i2c_dev_clk * 40) / (i2c_clk * 87) - 8; 317 low_reg = Std_low_count; 318 high_reg = Std_high_count; 319 } 320 else if (i2c_clk <= 400) // 400 kHz 321 { 322 low_count = (i2c_dev_clk * 13) / (i2c_clk * 19) - 1; 323 high_count = (i2c_dev_clk * 6) / (i2c_clk * 19) - 8; 324 low_reg = Fast_low_count; 325 high_reg = Fast_high_count; 326 } 327 else // > 400 kHz 328 { 329 // Note how the frequencies are scaled to accommodate the extra precision 330 // required. 331 332 low_count = (i2c_dev_clk / 10 * 50) / (i2c_clk / 10 * 76) - 1; 333 high_count = (i2c_dev_clk / 10 * 26) / (i2c_clk / 10 * 76) - 8; 334 low_reg = High_low_count; 335 high_reg = High_high_count; 336 } 337 338 // Minimum counts are 8 and 6 for low and high respectively. 339 340 _regs[low_reg] = low_count < 8 ? 8 : low_count; 341 _regs[high_reg] = high_count < 6 ? 6 : high_count; 342 343 //printf("low_count: %d\n", low_count); 344 //printf("high_count: %d\n", high_count); 345 346 // Data hold and setup times: 347 348 // Standard Fast High 349 // t{HD;DAT} 300ns 300ns 300ns 350 // t{SU;DAT} 250ns 100ns 50ns 351 352 // See: UM10204 "I2C-bus specification and user manual" 353 // Table 10: t{HD;DAT} and t{SU;DAT}, also note [3] 354 355 // T{delay} = (I2CSDAHD + 2) * T{I2C_DEV_CLK} 356 // I2CSDAHD = T{delay} / T{I2C_DEV_CLK} - 2 357 // I2CSDAHD = I2C_DEV_CLK * T{delay} - 2 358 359 // Since the device clock is in kHz (scaled down by 1000) and the times are 360 // given in ns (scaled up by 1000000000), a division of 1000000 is introduced. 361 362 hold_count = (i2c_dev_clk * 300) / 1000000 - 1; 363 364 _regs[I2c_sda_hold_time] = (_regs[I2c_sda_hold_time] & ~I2c_hold_mask) | 365 (hold_count < 0 ? 0 366 : (hold_count < (int) I2c_hold_mask ? (uint32_t) hold_count 367 : I2c_hold_mask)); 368 369 //printf("i2c_dev_clk: %d\n", i2c_dev_clk); 370 //printf("SDA hold: %x\n", hold_count); 371 372 // I2C_SDASU is apparently not used in master mode. 373 374 // T{delay} = (I2CSDASU - 1) * T{I2C_DEV_CLK} 375 // I2CSDASU = T{delay} / T{I2C_DEV_CLK} + 1 376 // I2CSDASU = I2C_DEV_CLK * T{delay} + 1 377 378 if (i2c_clk <= 100) 379 setup_count = (i2c_dev_clk * 250) / 1000000 + 1; 380 else if (i2c_clk <= 400) 381 setup_count = (i2c_dev_clk * 100) / 1000000 + 1; 382 else 383 setup_count = (i2c_dev_clk * 50) / 1000000 + 1; 384 385 _regs[I2c_sda_setup_time] = (_regs[I2c_sda_setup_time] & ~I2c_setup_mask) | 386 (setup_count < I2c_setup_mask ? setup_count : I2c_setup_mask); 387 } 388 389 // Set the target address and enable transfer. 390 // NOTE: Only supporting 7-bit addresses currently. 391 392 void 393 I2c_x1600_channel::set_target(uint8_t address) 394 { 395 //printf("set_target: %x\n", address); 396 _regs[I2c_target_address] = address & I2c_target_7bits; 397 init_parameters(); 398 //printf("I2c_enable_status: %x\n", (uint32_t) _regs[I2c_enable_status]); 399 //printf("I2c_status: %x\n", (uint32_t) _regs[I2c_status]); 400 //printf("Int_mask: %x\n", (uint32_t) _regs[Int_mask]); 401 //printf("Int_status: %x\n", (uint32_t) _regs[Int_status]); 402 //printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 403 } 404 405 406 407 // Reset interrupt flags upon certain conditions. 408 409 void 410 I2c_x1600_channel::reset_flags() 411 { 412 volatile uint32_t r; 413 414 _regs[Int_mask] = 0; 415 416 // Read from the register to clear interrupts. 417 418 r = _regs[Int_combined_clear]; 419 (void) r; 420 } 421 422 // Initialise interrupt flags and queue thresholds for reading and writing. 423 424 void 425 I2c_x1600_channel::init_parameters() 426 { 427 // Handle read queue conditions for data, write queue conditions for commands. 428 429 reset_flags(); 430 431 _regs[Tx_fifo_thold] = 0; // write when 0 in queue 432 } 433 434 435 436 // Return whether the device is active. 437 438 int 439 I2c_x1600_channel::active() 440 { 441 return _regs[I2c_status] & I2c_status_master_act; 442 } 443 444 // Return whether data is available to receive. 445 446 int 447 I2c_x1600_channel::have_input() 448 { 449 return _regs[I2c_status] & I2c_status_rx_nempty; 450 } 451 452 // Return whether data is queued for sending. 453 454 int 455 I2c_x1600_channel::have_output() 456 { 457 return !(_regs[I2c_status] & I2c_status_tx_empty); 458 } 459 460 // Return whether data can be queued for sending. 461 462 int 463 I2c_x1600_channel::can_send() 464 { 465 return _regs[I2c_status] & I2c_status_tx_nfull; 466 } 467 468 // Return whether a receive operation has failed. 469 470 int 471 I2c_x1600_channel::read_failed() 472 { 473 return _regs[Int_status] & Int_rx_of; 474 } 475 476 // Return whether a send operation has failed. 477 478 int 479 I2c_x1600_channel::write_failed() 480 { 481 return _regs[Int_status] & Int_tx_abort; 482 } 483 484 int 485 I2c_x1600_channel::read_done() 486 { 487 return _pos == _total; 488 } 489 490 int 491 I2c_x1600_channel::write_done() 492 { 493 return (_reqpos == _total) && !have_output(); 494 } 495 496 unsigned 497 I2c_x1600_channel::have_read() 498 { 499 return _pos; 500 } 501 502 unsigned 503 I2c_x1600_channel::have_written() 504 { 505 return _reqpos; 506 } 507 508 int 509 I2c_x1600_channel::failed() 510 { 511 return _fail; 512 } 513 514 515 516 // Send read commands for empty queue entries. 517 518 void 519 I2c_x1600_channel::queue_reads() 520 { 521 unsigned int remaining = _total - _reqpos; 522 unsigned int queued = _reqpos - _pos; 523 unsigned int can_queue = I2c_fifo_limit - queued; 524 525 // Keep the number of reads in progress below the length of the read queue. 526 527 if (!can_queue) 528 return; 529 530 // At most, only queue as many reads as are remaining. 531 532 if (remaining < can_queue) 533 can_queue = remaining; 534 535 // Queue read requests for any remaining queue entries. 536 537 while (can_queue && can_send()) 538 { 539 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 540 printf("Queue read %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); 541 542 _regs[I2c_data_command] = I2c_command_read | stop; 543 _reqpos++; 544 can_queue--; 545 } 546 547 // Update the threshold to be notified of any reduced remaining amount. 548 549 set_read_threshold(); 550 } 551 552 // Send write commands for empty queue entries. 553 554 void 555 I2c_x1600_channel::queue_writes() 556 { 557 unsigned int remaining = _total - _reqpos; 558 unsigned int can_queue = I2c_fifo_limit; 559 560 if (remaining < can_queue) 561 can_queue = remaining; 562 563 printf("queue_writes: %d %s\n", can_queue, can_send() ? "can send" : "cannot send"); 564 565 // Queue write requests for any remaining queue entries. 566 567 while (can_queue && can_send()) 568 { 569 uint32_t stop = _stop && (_reqpos == _total - 1) ? I2c_command_stop : I2c_command_no_stop; 570 printf("Queue write %d/%d %s\n", _reqpos, _total - 1, stop ? "stop" : "continue"); 571 572 _regs[I2c_data_command] = I2c_command_write | _buf[_reqpos] | stop; 573 _reqpos++; 574 can_queue--; 575 } 576 577 printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); 578 } 579 580 // Store read command results from the queue. 581 582 void 583 I2c_x1600_channel::store_reads() 584 { 585 printf("store_reads: %s\n", have_input() ? "input" : "no input"); 586 587 // Read any input and store it in the buffer. 588 589 while (have_input() && (_pos < _reqpos)) 590 { 591 _buf[_pos] = _regs[I2c_data_command] & 0xff; 592 _pos++; 593 } 594 } 595 596 void 597 I2c_x1600_channel::set_read_threshold() 598 { 599 unsigned int queued = _reqpos - _pos; 600 601 if (!queued) 602 return; 603 604 // Read all expected. 605 606 _regs[Rx_fifo_thold] = queued - 1; 607 printf("Rx_fifo_thold = %d\n", (uint32_t) _regs[Rx_fifo_thold]); 608 } 609 610 // Read from the target device. 611 612 void 613 I2c_x1600_channel::start_read(uint8_t buf[], unsigned int total, int stop) 614 { 615 _buf = buf; 616 _total = total; 617 _pos = 0; 618 _reqpos = 0; 619 _fail = 0; 620 _stop = stop; 621 622 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 623 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 624 printf("start_read: %d\n", total); 625 626 reset_flags(); 627 628 _regs[Int_mask] = Int_rx_full | // read condition (reading needed) 629 Int_rx_of | // abort condition 630 Int_tx_abort; // general abort condition 631 632 // Perform initial read requests. 633 634 read(); 635 } 636 637 void 638 I2c_x1600_channel::read() 639 { 640 printf("Rx_fifo_count = %d\n", (uint32_t) _regs[Rx_fifo_count]); 641 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 642 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 643 644 // Test for the general transfer abort condition. 645 646 if (read_failed() || write_failed()) 647 { 648 _fail = 1; 649 _regs[Int_mask] = 0; 650 return; 651 } 652 653 if (_regs[Int_status] & Int_rx_full) 654 store_reads(); 655 656 // Always attempt to queue more read requests. 657 658 queue_reads(); 659 } 660 661 // Write to the target device. 662 663 void 664 I2c_x1600_channel::start_write(uint8_t buf[], unsigned int total, int stop) 665 { 666 _buf = buf; 667 _total = total; 668 _reqpos = 0; 669 _fail = 0; 670 _stop = stop; 671 672 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 673 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 674 printf("start_write: %d\n", total); 675 676 reset_flags(); 677 678 // Enable interrupts for further writes. 679 680 _regs[Int_mask] = Int_tx_empty | // write condition (writing needed) 681 Int_tx_abort; // abort condition 682 683 // Perform initial writes. 684 685 write(); 686 } 687 688 void 689 I2c_x1600_channel::write() 690 { 691 printf("Tx_fifo_count = %d\n", (uint32_t) _regs[Tx_fifo_count]); 692 printf("Int_raw_status: %x\n", (uint32_t) _regs[Int_raw_status]); 693 printf("Trans_abort_status: %x\n", (uint32_t) _regs[Trans_abort_status]); 694 695 if (write_failed()) 696 { 697 _fail = 1; 698 _regs[Int_mask] = 0; 699 return; 700 } 701 702 if (_regs[Int_status] & Int_tx_empty) 703 queue_writes(); 704 } 705 706 // Explicitly stop communication. 707 708 void 709 I2c_x1600_channel::stop() 710 { 711 } 712 713 714 715 // Initialise the I2C controller. 716 717 I2c_x1600_chip::I2c_x1600_chip(l4_addr_t start, l4_addr_t end, 718 Cpm_x1600_chip *cpm, 719 uint32_t frequency) 720 : _start(start), _end(end), _cpm(cpm), _frequency(frequency) 721 { 722 } 723 724 // Obtain a channel object. 725 726 I2c_x1600_channel * 727 I2c_x1600_chip::get_channel(uint8_t channel) 728 { 729 l4_addr_t block = _start + channel * I2c_block_offset; 730 enum Clock_identifiers bits[] = {Clock_i2c0, Clock_i2c1}; 731 732 if (channel < 2) 733 { 734 _cpm->start_clock(bits[channel]); 735 return new I2c_x1600_channel(block, _cpm, _frequency); 736 } 737 else 738 throw -L4_EINVAL; 739 } 740 741 742 743 // C language interface functions. 744 745 void *x1600_i2c_init(l4_addr_t start, l4_addr_t end, void *cpm, uint32_t frequency) 746 { 747 return (void *) new I2c_x1600_chip(start, end, static_cast<Cpm_x1600_chip *>(cpm), frequency); 748 } 749 750 void x1600_i2c_disable(void *i2c_channel) 751 { 752 static_cast<I2c_x1600_channel *>(i2c_channel)->disable(); 753 } 754 755 void *x1600_i2c_get_channel(void *i2c, uint8_t channel) 756 { 757 return static_cast<I2c_x1600_chip *>(i2c)->get_channel(channel); 758 } 759 760 uint32_t x1600_i2c_get_frequency(void *i2c_channel) 761 { 762 return static_cast<I2c_x1600_channel *>(i2c_channel)->get_frequency(); 763 } 764 765 void x1600_i2c_set_target(void *i2c_channel, uint8_t addr) 766 { 767 static_cast<I2c_x1600_channel *>(i2c_channel)->set_target(addr); 768 } 769 770 void x1600_i2c_start_read(void *i2c_channel, uint8_t buf[], unsigned int total, 771 int stop) 772 { 773 static_cast<I2c_x1600_channel *>(i2c_channel)->start_read(buf, total, stop); 774 } 775 776 void x1600_i2c_read(void *i2c_channel) 777 { 778 static_cast<I2c_x1600_channel *>(i2c_channel)->read(); 779 } 780 781 void x1600_i2c_start_write(void *i2c_channel, uint8_t buf[], unsigned int total, 782 int stop) 783 { 784 static_cast<I2c_x1600_channel *>(i2c_channel)->start_write(buf, total, stop); 785 } 786 787 void x1600_i2c_write(void *i2c_channel) 788 { 789 static_cast<I2c_x1600_channel *>(i2c_channel)->write(); 790 } 791 792 int x1600_i2c_read_done(void *i2c_channel) 793 { 794 return static_cast<I2c_x1600_channel *>(i2c_channel)->read_done(); 795 } 796 797 int x1600_i2c_write_done(void *i2c_channel) 798 { 799 return static_cast<I2c_x1600_channel *>(i2c_channel)->write_done(); 800 } 801 802 unsigned int x1600_i2c_have_read(void *i2c_channel) 803 { 804 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_read(); 805 } 806 807 unsigned int x1600_i2c_have_written(void *i2c_channel) 808 { 809 return static_cast<I2c_x1600_channel *>(i2c_channel)->have_written(); 810 } 811 812 int x1600_i2c_failed(void *i2c_channel) 813 { 814 return static_cast<I2c_x1600_channel *>(i2c_channel)->failed(); 815 } 816 817 void x1600_i2c_stop(void *i2c_channel) 818 { 819 static_cast<I2c_x1600_channel *>(i2c_channel)->stop(); 820 }