1 /* 2 * GPIO driver for Ingenic JZ4780. 3 * (See below for additional copyright and licensing notices.) 4 * 5 * Copyright (C) 2017, 2023 Paul Boddie <paul@boddie.org.uk> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, 20 * Boston, MA 02110-1301, USA 21 * 22 * 23 * Subject to other copyrights, being derived from the bcm2835.cc and 24 * omap.cc GPIO driver implementations. 25 * 26 * This file is part of TUD:OS and distributed under the terms of the 27 * GNU General Public License 2. 28 * Please see the COPYING-GPL-2 file for details. 29 */ 30 31 #include <l4/sys/icu.h> 32 #include <l4/util/util.h> 33 #include <l4/devices/hw_mmio_register_block.h> 34 35 #include "gpio-jz4780.h" 36 37 /* 38 GPIO register offsets (x in A..F). 39 40 Register summary: 41 42 PxINT 0 (function/GPIO) 1 (interrupt) 43 PxMSK 0 (function) 1 (GPIO) 0 (IRQ enable)/1 (IRQ disable) 44 PxPAT1 0 (function 0/1) 1 (function 2/3) 0 (output) 1 (input) 0 (level trigger) 1 (edge trigger) 45 PxPAT0 0 (function 0) 0 (function 2) 0 (output value 0) 0 (low level) 0 (falling edge) 46 1 (function 1) 1 (function 3) 1 (output value 1) 1 (high level) 1 (rising edge) 47 */ 48 49 enum Regs 50 { 51 Pin_level = 0x000, // PxPIN (read-only) 52 53 Port_int = 0x010, // PxINT 54 Port_int_set = 0x014, // PxINTS 55 Port_int_clear = 0x018, // PxINTC 56 57 Irq_mask = 0x020, // PxMSK (for PxINT == 1) 58 Irq_mask_set = 0x024, // PxMSKS 59 Irq_mask_clear = 0x028, // PxMSKC 60 Port_gpio = 0x020, // PxMSK (for PxINT == 0) 61 Port_gpio_set = 0x024, // PxMSKS 62 Port_gpio_clear = 0x028, // PxMSKC 63 64 Port_trigger = 0x030, // PxPAT1 (for PxINT == 1) 65 Port_trigger_set = 0x034, // PxPAT1S 66 Port_trigger_clear = 0x038, // PxPAT1C 67 Port_dir = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 1) 68 Port_dir_set = 0x034, // PxPAT1S 69 Port_dir_clear = 0x038, // PxPAT1C 70 Port_group1 = 0x030, // PxPAT1 (for PxINT == 0, PxMSK == 0) 71 Port_group1_set = 0x034, // PxPAT1S 72 Port_group1_clear = 0x038, // PxPAT1C 73 74 Port_level = 0x040, // PxPAT0 (for PxINT == 1) 75 Port_level_set = 0x044, // PxPAT0S 76 Port_level_clear = 0x048, // PxPAT0C 77 Port_data = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 1, PxPAT1 == 0) 78 Port_data_set = 0x044, // PxPAT0S 79 Port_data_clear = 0x048, // PxPAT0C 80 Port_group0 = 0x040, // PxPAT0 (for PxINT == 0, PxMSK == 0) 81 Port_group0_set = 0x044, // PxPAT0S 82 Port_group0_clear = 0x048, // PxPAT0C 83 84 Irq_flag = 0x050, // PxFLG (read-only) 85 Irq_flag_clear = 0x058, // PxFLGC 86 87 Pull_disable = 0x070, // PxPE 88 Pull_disable_set = 0x074, // PxPES 89 Pull_disable_clear = 0x078, // PxPEC 90 }; 91 92 93 94 // JZ4780 pull-up/down configuration. 95 96 static struct gpio_port gpio_ports[] = { 97 {0x3fff00ff, 0x00000000}, 98 {0xfff0f3fc, 0x000f0c03}, 99 {0x0fffffff, 0x00000000}, 100 {0xffff4fff, 0x0000b000}, 101 {0xf0fff37c, 0x00000483}, 102 {0x7fa7f00f, 0x00580ff0}, 103 }; 104 105 106 107 // IRQ control for each GPIO pin. 108 109 Gpio_jz4780_irq_pin::Gpio_jz4780_irq_pin(unsigned pin, Hw::Register_block<32> const ®s) 110 : _pin(pin), _regs(regs) 111 {} 112 113 void 114 Gpio_jz4780_irq_pin::write_reg_pin(unsigned reg) 115 { 116 // Write the pin bit to the register, setting or clearing the pin 117 // depending on the register chosen. 118 119 _regs[reg] = _pin_bit(_pin); 120 } 121 122 void Gpio_jz4780_irq_pin::do_mask() 123 { 124 // Set the interrupt bit in the PxIM register. 125 126 write_reg_pin(Irq_mask_set); 127 } 128 129 void Gpio_jz4780_irq_pin::do_unmask() 130 { 131 // Clear the interrupt bit in the PxIM register, first also clearing the 132 // flag bit in the PxFLG register to allow interrupts to be delivered. 133 134 write_reg_pin(Irq_flag_clear); 135 write_reg_pin(Irq_mask_clear); 136 } 137 138 bool Gpio_jz4780_irq_pin::do_set_mode(unsigned mode) 139 { 140 // Standard comment found for this method: 141 // this operation touches multiple mmio registers and is thus 142 // not atomic, that's why we first mask the IRQ and if it was 143 // enabled we unmask it after we have changed the mode 144 145 if (enabled()) 146 do_mask(); 147 148 // Do the PxINT, PxPAT1 and PxPAT0 configuration. 149 150 switch(mode) 151 { 152 case L4_IRQ_F_LEVEL_HIGH: 153 write_reg_pin(Port_int_set); 154 write_reg_pin(Port_trigger_clear); 155 write_reg_pin(Port_level_set); 156 break; 157 case L4_IRQ_F_LEVEL_LOW: 158 write_reg_pin(Port_int_set); 159 write_reg_pin(Port_trigger_clear); 160 write_reg_pin(Port_level_clear); 161 break; 162 case L4_IRQ_F_POS_EDGE: 163 write_reg_pin(Port_int_set); 164 write_reg_pin(Port_trigger_set); 165 write_reg_pin(Port_level_set); 166 break; 167 case L4_IRQ_F_NEG_EDGE: 168 write_reg_pin(Port_int_set); 169 write_reg_pin(Port_trigger_set); 170 write_reg_pin(Port_level_clear); 171 break; 172 173 default: 174 return false; 175 } 176 177 if (enabled()) 178 do_unmask(); 179 180 return true; 181 } 182 183 int Gpio_jz4780_irq_pin::clear() 184 { 185 // Obtain the flag status for the pin, clearing it if set. 186 187 l4_uint32_t e = _regs[Irq_flag] & (1UL << _pin); 188 if (e) 189 _regs[Irq_flag_clear] = e; 190 191 return (e >> _pin); 192 } 193 194 bool Gpio_jz4780_irq_pin::enabled() 195 { 196 return true; 197 } 198 199 200 201 // Initialise the GPIO controller. 202 203 Gpio_jz4780_chip::Gpio_jz4780_chip(l4_addr_t start, uint8_t port_number) 204 : Hw::Gpio_chip(32) 205 { 206 _start = start + port_number * 0x100; 207 _regs = new Hw::Mmio_register_block<32>(_start); 208 _pull_config = &gpio_ports[port_number]; 209 } 210 211 // Return the value of a pin. 212 213 int 214 Gpio_jz4780_chip::get(unsigned pin) 215 { 216 if (pin >= _nr_pins) 217 throw -L4_EINVAL; 218 219 l4_uint32_t val = _regs[Pin_level]; 220 return (val >> _pin_shift(pin)) & 1; 221 } 222 223 // Return multiple pin values. 224 225 unsigned 226 Gpio_jz4780_chip::multi_get(unsigned offset) 227 { 228 _reg_offset_check(offset); 229 return _regs[Pin_level]; 230 } 231 232 // Set the value of a pin. 233 234 void 235 Gpio_jz4780_chip::set(unsigned pin, int value) 236 { 237 if (pin >= _nr_pins) 238 throw -L4_EINVAL; 239 240 l4_uint32_t reg_set = value ? Port_data_set : Port_data_clear; 241 _regs[reg_set] = _pin_bit(pin); 242 } 243 244 // Set multiple pin values. 245 246 void 247 Gpio_jz4780_chip::multi_set(Pin_slice const &mask, unsigned data) 248 { 249 _reg_offset_check(mask.offset); 250 if (mask.mask & data) 251 _regs[Port_data_set] = (mask.mask & data); 252 if (mask.mask & ~data) 253 _regs[Port_data_clear] = (mask.mask & ~data); 254 } 255 256 // Set a pin up with the given mode and value (if appropriate). 257 258 void 259 Gpio_jz4780_chip::setup(unsigned pin, unsigned mode, int value) 260 { 261 if (pin >= _nr_pins) 262 throw -L4_EINVAL; 263 264 config(pin, mode); 265 266 if (mode == Output) 267 set(pin, value); 268 } 269 270 // Configuration of a pin using the generic input/output/IRQ mode. 271 272 void 273 Gpio_jz4780_chip::config(unsigned pin, unsigned mode) 274 { 275 switch (mode) 276 { 277 case Input: 278 _regs[Port_int_clear] = _pin_bit(pin); 279 _regs[Port_gpio_set] = _pin_bit(pin); 280 _regs[Port_dir_set] = _pin_bit(pin); 281 break; 282 case Output: 283 _regs[Port_int_clear] = _pin_bit(pin); 284 _regs[Port_gpio_set] = _pin_bit(pin); 285 _regs[Port_dir_clear] = _pin_bit(pin); 286 break; 287 case Irq: 288 _regs[Port_int_set] = _pin_bit(pin); 289 // Other details depend on the actual trigger mode. 290 break; 291 default: 292 break; 293 } 294 } 295 296 // Pull-up/down configuration for a pin. 297 298 void 299 Gpio_jz4780_chip::config_pull(unsigned pin, unsigned mode) 300 { 301 if (pin >= _nr_pins) 302 throw -L4_EINVAL; 303 304 switch (mode) 305 { 306 case Pull_none: 307 _regs[Pull_disable_set] = _pin_bit(pin); 308 break; 309 case Pull_down: 310 if (_pin_bit(pin) & _pull_config->pull_downs) 311 _regs[Pull_disable_clear] = _pin_bit(pin); 312 break; 313 case Pull_up: 314 if (_pin_bit(pin) & _pull_config->pull_ups) 315 _regs[Pull_disable_clear] = _pin_bit(pin); 316 break; 317 default: 318 // Invalid pull-up/down mode for pin. 319 throw -L4_EINVAL; 320 } 321 } 322 323 // Pin function configuration. 324 325 void 326 Gpio_jz4780_chip::config_pad(unsigned pin, unsigned func, unsigned value) 327 { 328 if (pin >= _nr_pins) 329 throw -L4_EINVAL; 330 331 if (value > 3) 332 throw -L4_EINVAL; 333 334 switch (func) 335 { 336 // Support two different outputs. 337 338 case Hw::Gpio_chip::Function_gpio: 339 _regs[Port_int_clear] = _pin_bit(pin); 340 _regs[Port_gpio_set] = _pin_bit(pin); 341 _regs[value & 1 ? Port_data_set : Port_data_clear] = _pin_bit(pin); 342 break; 343 344 // Support four different device functions. 345 346 case Hw::Gpio_chip::Function_alt: 347 _regs[Port_int_clear] = _pin_bit(pin); 348 _regs[Port_gpio_clear] = _pin_bit(pin); 349 _regs[value & 2 ? Port_group1_set : Port_group1_clear] = _pin_bit(pin); 350 _regs[value & 1 ? Port_group0_set : Port_group0_clear] = _pin_bit(pin); 351 break; 352 default: 353 throw -L4_EINVAL; 354 } 355 } 356 357 // Obtain a pin's configuration from a register in the supplied value. 358 359 void 360 Gpio_jz4780_chip::config_get(unsigned pin, unsigned reg, unsigned *value) 361 { 362 if (pin >= _nr_pins) 363 throw -L4_EINVAL; 364 365 *value = (_regs[reg] >> _pin_shift(pin)) & 1; 366 } 367 368 // Return function and function-specific configuration for a pin. 369 370 void 371 Gpio_jz4780_chip::config_pad_get(unsigned pin, unsigned *func, unsigned *value) 372 { 373 unsigned direction, gpio, group0, group1, interrupt, level, trigger; 374 375 config_get(pin, Port_int, &interrupt); 376 377 if (interrupt) 378 { 379 config_get(pin, Port_trigger, &trigger); 380 config_get(pin, Port_level, &level); 381 382 *func = Hw::Gpio_chip::Function_irq; 383 *value = (trigger ? (level ? L4_IRQ_F_POS_EDGE : L4_IRQ_F_NEG_EDGE) 384 : (level ? L4_IRQ_F_LEVEL_HIGH : L4_IRQ_F_LEVEL_LOW)); 385 return; 386 } 387 388 config_get(pin, Port_gpio, &gpio); 389 390 if (gpio) 391 { 392 config_get(pin, Port_dir, &direction); 393 394 *func = Hw::Gpio_chip::Function_gpio; 395 *value = direction ? Input : Output; 396 return; 397 } 398 399 *func = Hw::Gpio_chip::Function_alt; 400 401 config_get(pin, Port_group0, &group0); 402 config_get(pin, Port_group1, &group1); 403 404 *value = (group1 << 1) | group0; 405 } 406 407 // Obtain an IRQ abstraction for a pin. 408 409 Hw::Gpio_irq_pin * 410 Gpio_jz4780_chip::get_irq(unsigned pin) 411 { 412 if (pin >= _nr_pins) 413 throw -L4_EINVAL; 414 415 return new Gpio_jz4780_irq_pin(pin, _regs); 416 } 417 418 // Pin function configuration for multiple pins. 419 420 void 421 Gpio_jz4780_chip::multi_config_pad(Pin_slice const &mask, unsigned func, unsigned val) 422 { 423 unsigned m = mask.mask; 424 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1) 425 if (m & 1) 426 config_pad(pin, func, val); 427 } 428 429 // Set up multiple pins with the given mode. 430 431 void 432 Gpio_jz4780_chip::multi_setup(Pin_slice const &mask, unsigned mode, unsigned outvalues) 433 { 434 unsigned m = mask.mask; 435 for (unsigned pin = mask.offset; pin < _nr_pins; ++pin, m >>= 1, outvalues >>= 1) 436 if (m & 1) 437 setup(pin, mode, outvalues & 1); 438 } 439 440 Hw::Gpio_chip *jz4780_gpio_chip(l4_addr_t start, uint8_t port_number, bool shadow) 441 { 442 (void) shadow; 443 return new Gpio_jz4780_chip(start, port_number); 444 } 445 446 447 448 // C language interface functions. 449 450 void *jz4780_gpio_init(l4_addr_t start, uint8_t port_number) 451 { 452 return (void *) jz4780_gpio_chip(start, port_number, false); 453 } 454 455 void jz4780_gpio_setup(void *gpio, unsigned pin, unsigned mode, int value) 456 { 457 static_cast<Gpio_jz4780_chip *>(gpio)->setup(pin, mode, value); 458 } 459 460 void jz4780_gpio_config_pull(void *gpio, unsigned pin, unsigned mode) 461 { 462 static_cast<Gpio_jz4780_chip *>(gpio)->config_pull(pin, mode); 463 } 464 465 void jz4780_gpio_config_pad(void *gpio, unsigned pin, unsigned func, unsigned value) 466 { 467 static_cast<Gpio_jz4780_chip *>(gpio)->config_pad(pin, func, value); 468 } 469 470 void jz4780_gpio_config_get(void *gpio, unsigned pin, unsigned reg, unsigned *value) 471 { 472 static_cast<Gpio_jz4780_chip *>(gpio)->config_get(pin, reg, value); 473 } 474 475 void jz4780_gpio_config_pad_get(void *gpio, unsigned pin, unsigned *func, unsigned *value) 476 { 477 static_cast<Gpio_jz4780_chip *>(gpio)->config_pad_get(pin, func, value); 478 } 479 480 void jz4780_gpio_multi_setup(void *gpio, Pin_slice const *mask, unsigned mode, unsigned outvalues) 481 { 482 static_cast<Gpio_jz4780_chip *>(gpio)->multi_setup(*mask, mode, outvalues); 483 } 484 485 void jz4780_gpio_multi_config_pad(void *gpio, Pin_slice const *mask, unsigned func, unsigned value) 486 { 487 static_cast<Gpio_jz4780_chip *>(gpio)->multi_config_pad(*mask, func, value); 488 } 489 490 void jz4780_gpio_multi_set(void *gpio, Pin_slice const *mask, unsigned data) 491 { 492 static_cast<Gpio_jz4780_chip *>(gpio)->multi_set(*mask, data); 493 } 494 495 unsigned jz4780_gpio_multi_get(void *gpio, unsigned offset) 496 { 497 return static_cast<Gpio_jz4780_chip *>(gpio)->multi_get(offset); 498 } 499 500 int jz4780_gpio_get(void *gpio, unsigned pin) 501 { 502 return static_cast<Gpio_jz4780_chip *>(gpio)->get(pin); 503 } 504 505 void jz4780_gpio_set(void *gpio, unsigned pin, int value) 506 { 507 static_cast<Gpio_jz4780_chip *>(gpio)->set(pin, value); 508 } 509 510 void *jz4780_gpio_get_irq(void *gpio, unsigned pin) 511 { 512 return (void *) static_cast<Gpio_jz4780_chip *>(gpio)->get_irq(pin); 513 } 514 515 bool jz4780_gpio_irq_set_mode(void *gpio_irq, unsigned mode) 516 { 517 return static_cast<Hw::Gpio_irq_pin *>(gpio_irq)->do_set_mode(mode); 518 }