1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 02:21:50 2023 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Mon Sep 18 16:40:15 2023 +0200
1.3 @@ -255,125 +255,126 @@
1.4 // Note the use of extra parentheses due to the annoying C++ "most vexing parse"
1.5 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
1.6
1.7 -static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
1.8 +static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
1.9 +
1.10 + clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))),
1.11 +
1.12 + clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.13 +
1.14 + clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.15 +
1.16 + clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
1.17 +
1.18 + clock_main(Source(mux_core, Clock_source_main), Control(Clock_gate_main)),
1.19 +
1.20 + clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
1.21 +
1.22 + clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
1.23 +
1.24 + clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))),
1.25 +
1.26 + clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))),
1.27 +
1.28 + clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3)));
1.29 +
1.30 +static Clock_divided
1.31 + clock_can0(Source(mux_bus, Clock_source_can0),
1.32 + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
1.33 + Divider(Clock_divider_can0)),
1.34 +
1.35 + clock_can1(Source(mux_bus, Clock_source_can1),
1.36 + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
1.37 + Divider(Clock_divider_can1)),
1.38 +
1.39 + clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.40 + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
1.41 + Divider(Clock_divider_cdbus)),
1.42 +
1.43 + clock_cim(Source(mux_dev, Clock_source_cim),
1.44 + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
1.45 + Divider(Clock_divider_cim)),
1.46 +
1.47 + clock_cpu(Source(mux_core, Clock_source_cpu),
1.48 + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
1.49 + Divider(Clock_divider_cpu)),
1.50 +
1.51 + clock_ddr(Source(mux_core, Clock_source_ddr),
1.52 + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
1.53 + Divider(Clock_divider_ddr)),
1.54 +
1.55 + clock_hclock0(Source(mux_core, Clock_source_hclock0),
1.56 + Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.57 + Divider(Clock_divider_hclock0)),
1.58 +
1.59 + clock_hclock2(Source(mux_ahb2_apb),
1.60 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.61 + Divider(Clock_divider_hclock2)),
1.62 +
1.63 + clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
1.64 + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
1.65 + Divider(Clock_divider_lcd)),
1.66
1.67 - clock_dma((Source(mux_pclock)), (Control(Clock_gate_dma))),
1.68 -
1.69 - clock_i2c((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.70 -
1.71 - clock_i2c0((Source(mux_pclock)), (Control(Clock_gate_i2c0))),
1.72 -
1.73 - clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
1.74 -
1.75 - clock_main(Source(mux_core, Clock_source_main),
1.76 - Control(Clock_gate_main)),
1.77 -
1.78 - clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
1.79 -
1.80 - clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
1.81 -
1.82 - clock_uart1((Source(mux_external)), (Control(Clock_gate_uart1))),
1.83 -
1.84 - clock_uart2((Source(mux_external)), (Control(Clock_gate_uart2))),
1.85 -
1.86 - clock_uart3((Source(mux_external)), (Control(Clock_gate_uart3)));
1.87 -
1.88 -static Clock_divided clock_can0(Source(mux_bus, Clock_source_can0),
1.89 - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
1.90 - Divider(Clock_divider_can0)),
1.91 -
1.92 - clock_can1(Source(mux_bus, Clock_source_can1),
1.93 - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
1.94 - Divider(Clock_divider_can1)),
1.95 -
1.96 - clock_cdbus(Source(mux_dev, Clock_source_cdbus),
1.97 - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
1.98 - Divider(Clock_divider_cdbus)),
1.99 -
1.100 - clock_cim(Source(mux_dev, Clock_source_cim),
1.101 - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
1.102 - Divider(Clock_divider_cim)),
1.103 -
1.104 - clock_cpu(Source(mux_core, Clock_source_cpu),
1.105 - Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
1.106 - Divider(Clock_divider_cpu)),
1.107 -
1.108 - clock_ddr(Source(mux_core, Clock_source_ddr),
1.109 - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
1.110 - Divider(Clock_divider_ddr)),
1.111 -
1.112 - clock_hclock0(Source(mux_core, Clock_source_hclock0),
1.113 - Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
1.114 - Divider(Clock_divider_hclock0)),
1.115 -
1.116 - clock_hclock2(Source(mux_ahb2_apb),
1.117 - Control(Clock_gate_apb0, Clock_change_enable_ahb2),
1.118 - Divider(Clock_divider_hclock2)),
1.119 -
1.120 - clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
1.121 - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
1.122 - Divider(Clock_divider_lcd)),
1.123 -
1.124 - clock_mac(Source(mux_dev, Clock_source_mac),
1.125 - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
1.126 - Divider(Clock_divider_mac)),
1.127 -
1.128 - clock_msc(Source(mux_dev, Clock_source_msc0),
1.129 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.130 - Divider(Clock_divider_msc0)),
1.131 -
1.132 - clock_msc0(Source(mux_dev, Clock_source_msc0),
1.133 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.134 - Divider(Clock_divider_msc0)),
1.135 -
1.136 - clock_msc1(Source(mux_dev, Clock_source_msc1),
1.137 - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.138 - Divider(Clock_divider_msc1)),
1.139 -
1.140 - clock_pclock((Source(mux_ahb2_apb)),
1.141 - (Control(Clock_gate_apb0)),
1.142 - (Divider(Clock_divider_pclock))),
1.143 -
1.144 - clock_pwm(Source(mux_dev, Clock_source_pwm),
1.145 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.146 - Divider(Clock_divider_pwm)),
1.147 -
1.148 - clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.149 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.150 - Divider(Clock_divider_pwm)),
1.151 -
1.152 - clock_sfc(Source(mux_dev, Clock_source_sfc),
1.153 - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
1.154 - Divider(Clock_divider_sfc)),
1.155 -
1.156 - clock_ssi(Source(mux_dev, Clock_source_ssi),
1.157 - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
1.158 - Divider(Clock_divider_ssi));
1.159 -
1.160 -static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.161 - Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
1.162 - Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.163 - Clock_divider_i2s0_d)),
1.164 + clock_mac(Source(mux_dev, Clock_source_mac),
1.165 + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
1.166 + Divider(Clock_divider_mac)),
1.167 +
1.168 + clock_msc(Source(mux_dev, Clock_source_msc0),
1.169 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.170 + Divider(Clock_divider_msc0)),
1.171 +
1.172 + clock_msc0(Source(mux_dev, Clock_source_msc0),
1.173 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
1.174 + Divider(Clock_divider_msc0)),
1.175 +
1.176 + clock_msc1(Source(mux_dev, Clock_source_msc1),
1.177 + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
1.178 + Divider(Clock_divider_msc1)),
1.179 +
1.180 + clock_pclock((Source(mux_ahb2_apb)),
1.181 + (Control(Clock_gate_apb0)),
1.182 + (Divider(Clock_divider_pclock))),
1.183 +
1.184 + clock_pwm(Source(mux_dev, Clock_source_pwm),
1.185 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.186 + Divider(Clock_divider_pwm)),
1.187 +
1.188 + clock_pwm0(Source(mux_dev, Clock_source_pwm),
1.189 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
1.190 + Divider(Clock_divider_pwm)),
1.191
1.192 - clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
1.193 - Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
1.194 - Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.195 - Clock_divider_i2s1_d));
1.196 + clock_sfc(Source(mux_dev, Clock_source_sfc),
1.197 + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
1.198 + Divider(Clock_divider_sfc)),
1.199
1.200 -static Pll clock_pll_A(Source(mux_external),
1.201 - Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.202 - Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.203 - Pll_output_division0_A, Pll_output_division1_A)),
1.204 + clock_ssi(Source(mux_dev, Clock_source_ssi),
1.205 + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
1.206 + Divider(Clock_divider_ssi));
1.207 +
1.208 +static Clock_divided_i2s
1.209 + clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
1.210 + Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
1.211 + Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.212 + Clock_divider_i2s0_d)),
1.213
1.214 - clock_pll_E(Source(mux_external),
1.215 - Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.216 - Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.217 - Pll_output_division0_E, Pll_output_division1_E)),
1.218 + clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
1.219 + Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
1.220 + Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.221 + Clock_divider_i2s1_d));
1.222 +
1.223 +static Pll clock_pll_A(Source(mux_external),
1.224 + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
1.225 + Divider_pll(Pll_multiplier_A, Pll_input_division_A,
1.226 + Pll_output_division0_A, Pll_output_division1_A)),
1.227
1.228 - clock_pll_M(Source(mux_external),
1.229 - Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.230 - Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.231 - Pll_output_division0_M, Pll_output_division1_M));
1.232 + clock_pll_E(Source(mux_external),
1.233 + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
1.234 + Divider_pll(Pll_multiplier_E, Pll_input_division_E,
1.235 + Pll_output_division0_E, Pll_output_division1_E)),
1.236 +
1.237 + clock_pll_M(Source(mux_external),
1.238 + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
1.239 + Divider_pll(Pll_multiplier_M, Pll_input_division_M,
1.240 + Pll_output_division0_M, Pll_output_division1_M));
1.241
1.242
1.243
1.244 @@ -601,31 +602,31 @@
1.245
1.246 int
1.247 x1600_cpm_get_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[])
1.248 -{
1.249 +{
1.250 return static_cast<Cpm_x1600_chip *>(cpm)->get_parameters(clock, parameters);
1.251 }
1.252
1.253 void
1.254 x1600_cpm_set_parameters(void *cpm, enum Clock_identifiers clock, uint32_t parameters[])
1.255 -{
1.256 +{
1.257 return static_cast<Cpm_x1600_chip *>(cpm)->set_parameters(clock, parameters);
1.258 }
1.259
1.260 uint8_t
1.261 x1600_cpm_get_source(void *cpm, enum Clock_identifiers clock)
1.262 -{
1.263 +{
1.264 return static_cast<Cpm_x1600_chip *>(cpm)->get_source(clock);
1.265 }
1.266
1.267 void
1.268 x1600_cpm_set_source(void *cpm, enum Clock_identifiers clock, uint8_t source)
1.269 -{
1.270 +{
1.271 static_cast<Cpm_x1600_chip *>(cpm)->set_source(clock, source);
1.272 }
1.273
1.274 uint32_t
1.275 x1600_cpm_get_source_frequency(void *cpm, enum Clock_identifiers clock)
1.276 -{
1.277 +{
1.278 return static_cast<Cpm_x1600_chip *>(cpm)->get_source_frequency(clock);
1.279 }
1.280