1.1 --- a/pkg/devices/include/clocks.h Thu Nov 16 17:48:32 2023 +0100
1.2 +++ b/pkg/devices/include/clocks.h Thu Nov 16 22:03:51 2023 +0100
1.3 @@ -39,6 +39,7 @@
1.4 Clock_dma,
1.5 Clock_emac,
1.6 Clock_external, /* EXCLK */
1.7 + Clock_external_div_512,
1.8 Clock_hclock0, /* AHB0 */
1.9 Clock_hclock2, /* AHB2 */
1.10 Clock_hclock2_pclock, /* AHB2, APB parent clock (JZ4780, X1600) */
1.11 @@ -76,7 +77,8 @@
1.12 Clock_pll_V,
1.13 Clock_pwm0,
1.14 Clock_pwm1,
1.15 - Clock_rtc, /* RTCLK */
1.16 + Clock_rtc, /* RTC parent clock */
1.17 + Clock_rtc_external, /* RTCLK */
1.18 Clock_scc,
1.19 Clock_sfc,
1.20 Clock_ssi, /* SSI parent clock (JZ4780) */
2.1 --- a/pkg/devices/lib/cpm/include/cpm-common.h Thu Nov 16 17:48:32 2023 +0100
2.2 +++ b/pkg/devices/lib/cpm/include/cpm-common.h Thu Nov 16 22:03:51 2023 +0100
2.3 @@ -275,8 +275,32 @@
2.4 // Other operations.
2.5
2.6 virtual int get_parameters(Cpm_regs ®s, uint32_t parameters[]) = 0;
2.7 + virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0;
2.8 +};
2.9
2.10 - virtual int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]) = 0;
2.11 +
2.12 +
2.13 +// Fixed divider.
2.14 +
2.15 +class Divider_fixed : public Divider_base
2.16 +{
2.17 + uint32_t _value;
2.18 +
2.19 +public:
2.20 + explicit Divider_fixed(uint32_t value)
2.21 + : _value(value)
2.22 + {
2.23 + }
2.24 +
2.25 + // Output frequency.
2.26 +
2.27 + uint64_t get_frequency(Cpm_regs ®s, uint64_t source_frequency);
2.28 + int set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency);
2.29 +
2.30 + // Other operations.
2.31 +
2.32 + int get_parameters(Cpm_regs ®s, uint32_t parameters[]);
2.33 + int set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[]);
2.34 };
2.35
2.36
2.37 @@ -631,6 +655,27 @@
2.38
2.39
2.40
2.41 +// Fixed divider clock description.
2.42 +
2.43 +class Clock_divided_fixed : public Clock_divided_base
2.44 +{
2.45 + Control _control;
2.46 + Divider_fixed _divider;
2.47 +
2.48 + virtual Control_base &_get_control() { return _control; }
2.49 + virtual Divider_base &_get_divider() { return _divider; }
2.50 +
2.51 +public:
2.52 + explicit Clock_divided_fixed(Source source, Divider_fixed divider)
2.53 + : Clock_divided_base(source), _control(Control::undefined), _divider(divider)
2.54 + {
2.55 + }
2.56 +
2.57 + const char *clock_type() { return "fix_div"; }
2.58 +};
2.59 +
2.60 +
2.61 +
2.62 // I2S clock description.
2.63
2.64 class Clock_divided_i2s : public Clock_divided_base
3.1 --- a/pkg/devices/lib/cpm/src/common.cc Thu Nov 16 17:48:32 2023 +0100
3.2 +++ b/pkg/devices/lib/cpm/src/common.cc Thu Nov 16 22:03:51 2023 +0100
3.3 @@ -301,6 +301,41 @@
3.4
3.5
3.6
3.7 +// Fixed divider.
3.8 +
3.9 +uint64_t
3.10 +Divider_fixed::get_frequency(Cpm_regs ®s, uint64_t source_frequency)
3.11 +{
3.12 + (void) regs;
3.13 + return source_frequency / _value;
3.14 +}
3.15 +
3.16 +int
3.17 +Divider_fixed::set_frequency(Cpm_regs ®s, uint64_t source_frequency, uint64_t frequency)
3.18 +{
3.19 + (void) regs; (void) source_frequency; (void) frequency;
3.20 + return 0;
3.21 +}
3.22 +
3.23 +int
3.24 +Divider_fixed::get_parameters(Cpm_regs ®s, uint32_t parameters[])
3.25 +{
3.26 + (void) regs;
3.27 + parameters[0] = _value;
3.28 + return 1;
3.29 +}
3.30 +
3.31 +int
3.32 +Divider_fixed::set_parameters(Cpm_regs ®s, int num_parameters, uint32_t parameters[])
3.33 +{
3.34 + (void) regs; (void) num_parameters; (void) parameters;
3.35 + return 0;
3.36 +}
3.37 +
3.38 +
3.39 +
3.40 +// Simple divider for regular clocks.
3.41 +
3.42 uint32_t
3.43 Divider::get_divider(Cpm_regs ®s)
3.44 {
4.1 --- a/pkg/devices/lib/cpm/src/jz4780.cc Thu Nov 16 17:48:32 2023 +0100
4.2 +++ b/pkg/devices/lib/cpm/src/jz4780.cc Thu Nov 16 22:03:51 2023 +0100
4.3 @@ -252,9 +252,9 @@
4.4
4.5 // Main bus and peripheral clock sources.
4.6
4.7 - mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc)),
4.8 + mux_ahb2 (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_rtc_external)),
4.9 mux_core (4, Clocks(Clock_none, Clock_main, Clock_pll_M, Clock_pll_E)),
4.10 - mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc)),
4.11 + mux_main (4, Clocks(Clock_none, Clock_pll_A, Clock_external, Clock_rtc_external)),
4.12
4.13 // Memory and device clock sources.
4.14
4.15 @@ -276,7 +276,8 @@
4.16
4.17 static Clock_null clock_none;
4.18
4.19 -static Clock_passive clock_external(48000000), clock_rtc(32768);
4.20 +static Clock_passive clock_external(48000000),
4.21 + clock_rtc_external(32768);
4.22
4.23
4.24
4.25 @@ -432,6 +433,9 @@
4.26 Control(Clock_gate_vpu, Clock_change_enable_vpu, Clock_busy_vpu),
4.27 Divider(Clock_divider_vpu));
4.28
4.29 +static Clock_divided_fixed
4.30 + clock_external_div_512((Source(mux_external)), (Divider_fixed(512)));
4.31 +
4.32 const double jz4780_pll_intermediate_min = 300000000,
4.33 jz4780_pll_intermediate_max = 1500000000;
4.34
4.35 @@ -480,6 +484,7 @@
4.36 &clock_dma,
4.37 &clock_none, // Clock_emac
4.38 &clock_external,
4.39 + &clock_external_div_512,
4.40 &clock_hclock0,
4.41 &clock_hclock2,
4.42 &clock_hclock2_pclock,
4.43 @@ -517,7 +522,8 @@
4.44 &clock_pll_V,
4.45 &clock_none, // Clock_pwm0
4.46 &clock_none, // Clock_pwm1
4.47 - &clock_rtc,
4.48 + &clock_external_div_512,// Clock_rtc
4.49 + &clock_rtc_external,
4.50 &clock_scc,
4.51 &clock_none, // Clock_sfc
4.52 &clock_ssi,
5.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Nov 16 17:48:32 2023 +0100
5.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Nov 16 22:03:51 2023 +0100
5.3 @@ -97,6 +97,7 @@
5.4 Clock_source_msc0 (Divider_msc0, 3, 30), // MPCS
5.5 Clock_source_msc1 (Divider_msc1, 3, 30), // MPCS
5.6 Clock_source_pwm (Divider_pwm, 3, 30), // PWMPCS
5.7 + Clock_source_rtc (Sleep_control, 0x01, 2), // ERCS
5.8 Clock_source_sfc (Divider_sfc, 3, 30), // SFCS
5.9 Clock_source_ssi (Divider_ssi, 3, 30), // SPCS
5.10
5.11 @@ -254,7 +255,8 @@
5.12 mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)),
5.13 mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)),
5.14 mux_main (3, Clocks(Clock_none, Clock_external, Clock_pll_A)),
5.15 - mux_i2s (2, Clocks(Clock_main, Clock_pll_E));
5.16 + mux_i2s (2, Clocks(Clock_main, Clock_pll_E)),
5.17 + mux_rtc (2, Clocks(Clock_external_div_512, Clock_rtc_external));
5.18
5.19
5.20
5.21 @@ -262,7 +264,8 @@
5.22
5.23 static Clock_null clock_none;
5.24
5.25 -static Clock_passive clock_external(24000000);
5.26 +static Clock_passive clock_external(24000000),
5.27 + clock_rtc_external(32768);
5.28
5.29 // Note the use of extra parentheses due to the annoying C++ "most vexing parse"
5.30 // problem. See: https://en.wikipedia.org/wiki/Most_vexing_parse
5.31 @@ -285,6 +288,8 @@
5.32
5.33 clock_otg0((Source(mux_hclock2)), (Control(Clock_gate_otg))),
5.34
5.35 + clock_rtc(Source(mux_rtc, Clock_source_rtc), (Control(Clock_gate_rtc))),
5.36 +
5.37 clock_timer((Source(mux_pclock)), (Control(Clock_gate_timer))),
5.38
5.39 clock_uart0((Source(mux_external)), (Control(Clock_gate_uart0))),
5.40 @@ -361,6 +366,9 @@
5.41 Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
5.42 Divider(Clock_divider_ssi));
5.43
5.44 +static Clock_divided_fixed
5.45 + clock_external_div_512((Source(mux_external)), (Divider_fixed(512)));
5.46 +
5.47 static Clock_divided_i2s
5.48 clock_i2s0_rx(Source(mux_i2s0_rx),
5.49 Control(Clock_gate_i2s0_rx),
5.50 @@ -415,6 +423,7 @@
5.51 &clock_dma,
5.52 &clock_none, // Clock_emac
5.53 &clock_external,
5.54 + &clock_external_div_512,
5.55 &clock_hclock0,
5.56 &clock_hclock2,
5.57 &clock_hclock2_pclock,
5.58 @@ -452,7 +461,8 @@
5.59 &clock_none, // Clock_pll_V
5.60 &clock_pwm0,
5.61 &clock_none, // Clock_pwm1
5.62 - &clock_none, // Clock_rtc
5.63 + &clock_rtc,
5.64 + &clock_rtc_external,
5.65 &clock_none, // Clock_scc
5.66 &clock_sfc,
5.67 &clock_none, // Clock_ssi
6.1 --- a/pkg/landfall-examples/hw_info/common.h Thu Nov 16 17:48:32 2023 +0100
6.2 +++ b/pkg/landfall-examples/hw_info/common.h Thu Nov 16 22:03:51 2023 +0100
6.3 @@ -173,6 +173,10 @@
6.4
6.5 void rtc_enable(void *rtc);
6.6
6.7 +void rtc_alarm_disable(void *rtc);
6.8 +
6.9 +void rtc_alarm_enable(void *rtc);
6.10 +
6.11 uint32_t rtc_get_seconds(void *rtc);
6.12
6.13 void rtc_set_seconds(void *rtc, uint32_t seconds);
7.1 --- a/pkg/landfall-examples/hw_info/hw_info.c Thu Nov 16 17:48:32 2023 +0100
7.2 +++ b/pkg/landfall-examples/hw_info/hw_info.c Thu Nov 16 22:03:51 2023 +0100
7.3 @@ -334,11 +334,11 @@
7.4 {
7.5 /* Read information from the clock and power management unit. */
7.6
7.7 - printf("%-5s %-10s %-7s %-6s %-12s %-12s %-24s %-12s %-3s\n"
7.8 - "%-5s %-10s %-7s %-6s %-12s %-12s %-24s %-12s %-3s\n",
7.9 + printf("%-10s %-15s %-7s %-6s %-12s %-12s %-24s %-12s %-3s\n"
7.10 + "%-10s %-15s %-7s %-6s %-12s %-12s %-24s %-12s %-3s\n",
7.11 "Id", "Clock", "Type", "Source", "Source Clock", "Source Freq.",
7.12 "Parameters", "Frequency", "On",
7.13 - sep(5), sep(10), sep(7), sep(6), sep(12), sep(12),
7.14 + sep(10), sep(15), sep(7), sep(6), sep(12), sep(12),
7.15 sep(24), sep(12), sep(3));
7.16
7.17 for (int i = 0; clocks[i].id != NULL; i++)
7.18 @@ -356,7 +356,7 @@
7.19 pos += result;
7.20 }
7.21
7.22 - printf("%-5s %-10s %-7s %-6d %-12s %-12lld %-24s %-12lld %-3s\n",
7.23 + printf("%-10s %-15s %-7s %-6d %-12s %-12lld %-24s %-12lld %-3s\n",
7.24 clocks[i].id,
7.25 clocks[i].name,
7.26 cpm_clock_type(cpm, clocks[i].clock),
7.27 @@ -1127,6 +1127,7 @@
7.28 uint32_t rtc_seconds = rtc_get_seconds(rtc);
7.29 uint32_t value = seconds * cpm_get_frequency(cpm, Clock_external) / 512;
7.30
7.31 + rtc_alarm_disable(rtc);
7.32 rtc_set_alarm_seconds(rtc, rtc_seconds + value);
7.33 rtc_hibernate(rtc);
7.34 }
8.1 --- a/pkg/landfall-examples/hw_info/jz4780.c Thu Nov 16 17:48:32 2023 +0100
8.2 +++ b/pkg/landfall-examples/hw_info/jz4780.c Thu Nov 16 22:03:51 2023 +0100
8.3 @@ -352,6 +352,16 @@
8.4 x1600_rtc_enable(rtc);
8.5 }
8.6
8.7 +void rtc_alarm_disable(void *rtc)
8.8 +{
8.9 + x1600_rtc_alarm_disable(rtc);
8.10 +}
8.11 +
8.12 +void rtc_alarm_enable(void *rtc)
8.13 +{
8.14 + x1600_rtc_alarm_enable(rtc);
8.15 +}
8.16 +
8.17 uint32_t rtc_get_seconds(void *rtc)
8.18 {
8.19 return x1600_rtc_get_seconds(rtc);
8.20 @@ -476,45 +486,48 @@
8.21 /* CPM definitions. */
8.22
8.23 struct clock_info clocks[] = {
8.24 - {"ext", Clock_external, "External"},
8.25 - {"plla", Clock_pll_A, "PLL A"},
8.26 - {"plle", Clock_pll_E, "PLL E"},
8.27 - {"pllm", Clock_pll_M, "PLL M"},
8.28 - {"pllv", Clock_pll_V, "PLL V"},
8.29 - {"main", Clock_main, "Main"},
8.30 - {"cpu", Clock_cpu, "CPU"},
8.31 - {"h2p", Clock_hclock2_pclock, "AHB2/APB"},
8.32 - {"ahb0", Clock_hclock0, "AHB0"},
8.33 - {"ahb2", Clock_hclock2, "AHB2"},
8.34 - {"apb", Clock_pclock, "APB"},
8.35 - {"dma", Clock_dma, "DMA"},
8.36 - {"hdmi", Clock_lcd, "HDMI"},
8.37 - {"lcd", Clock_lcd, "LCD"},
8.38 - {"lcd0", Clock_lcd_pixel0, "LCD0 pixel"},
8.39 - {"lcd1", Clock_lcd_pixel1, "LCD1 pixel"},
8.40 - {"msc", Clock_msc, "MSC"},
8.41 - {"msc0", Clock_msc0, "MSC0"},
8.42 - {"msc1", Clock_msc1, "MSC1"},
8.43 - {"msc2", Clock_msc1, "MSC2"},
8.44 - {"otg0", Clock_otg0, "USB OTG0"},
8.45 - {"otg1", Clock_otg1, "USB OTG1"},
8.46 - {"i2c0", Clock_i2c0, "I2C0"},
8.47 - {"i2c1", Clock_i2c1, "I2C1"},
8.48 - {"i2c2", Clock_i2c2, "I2C2"},
8.49 - {"i2c3", Clock_i2c3, "I2C3"},
8.50 - {"i2c4", Clock_i2c4, "I2C4"},
8.51 - {"i2s0", Clock_i2s0, "I2S0"},
8.52 - {"i2s1", Clock_i2s1, "I2S1"},
8.53 - {"pcm", Clock_pcm, "PCM"},
8.54 - {"ssi", Clock_ssi, "SSI"},
8.55 - {"ssi0", Clock_ssi0, "SSI0"},
8.56 - {"ssi1", Clock_ssi1, "SSI1"},
8.57 - {"uart0", Clock_uart0, "UART0"},
8.58 - {"uart1", Clock_uart1, "UART1"},
8.59 - {"uart2", Clock_uart2, "UART2"},
8.60 - {"uart3", Clock_uart3, "UART3"},
8.61 - {"uart4", Clock_uart4, "UART4"},
8.62 - {NULL, Clock_undefined, NULL},
8.63 + {"ext", Clock_external, "EXCLK"},
8.64 + {"ext_512", Clock_external_div_512, "EXCLK/512"},
8.65 + {"rtc_ext", Clock_rtc_external, "RTCLK"},
8.66 + {"plla", Clock_pll_A, "PLL A"},
8.67 + {"plle", Clock_pll_E, "PLL E"},
8.68 + {"pllm", Clock_pll_M, "PLL M"},
8.69 + {"pllv", Clock_pll_V, "PLL V"},
8.70 + {"main", Clock_main, "Main (SCLK_A)"},
8.71 + {"cpu", Clock_cpu, "CPU"},
8.72 + {"h2p", Clock_hclock2_pclock, "AHB2/APB"},
8.73 + {"ahb0", Clock_hclock0, "AHB0"},
8.74 + {"ahb2", Clock_hclock2, "AHB2"},
8.75 + {"apb", Clock_pclock, "APB"},
8.76 + {"dma", Clock_dma, "DMA"},
8.77 + {"hdmi", Clock_lcd, "HDMI"},
8.78 + {"lcd", Clock_lcd, "LCD"},
8.79 + {"lcd0", Clock_lcd_pixel0, "LCD0 pixel"},
8.80 + {"lcd1", Clock_lcd_pixel1, "LCD1 pixel"},
8.81 + {"msc", Clock_msc, "MSC"},
8.82 + {"msc0", Clock_msc0, "MSC0"},
8.83 + {"msc1", Clock_msc1, "MSC1"},
8.84 + {"msc2", Clock_msc1, "MSC2"},
8.85 + {"otg0", Clock_otg0, "USB OTG0"},
8.86 + {"otg1", Clock_otg1, "USB OTG1"},
8.87 + {"i2c0", Clock_i2c0, "I2C0"},
8.88 + {"i2c1", Clock_i2c1, "I2C1"},
8.89 + {"i2c2", Clock_i2c2, "I2C2"},
8.90 + {"i2c3", Clock_i2c3, "I2C3"},
8.91 + {"i2c4", Clock_i2c4, "I2C4"},
8.92 + {"i2s0", Clock_i2s0, "I2S0"},
8.93 + {"i2s1", Clock_i2s1, "I2S1"},
8.94 + {"pcm", Clock_pcm, "PCM"},
8.95 + {"rtc", Clock_rtc, "RTC"},
8.96 + {"ssi", Clock_ssi, "SSI"},
8.97 + {"ssi0", Clock_ssi0, "SSI0"},
8.98 + {"ssi1", Clock_ssi1, "SSI1"},
8.99 + {"uart0", Clock_uart0, "UART0"},
8.100 + {"uart1", Clock_uart1, "UART1"},
8.101 + {"uart2", Clock_uart2, "UART2"},
8.102 + {"uart3", Clock_uart3, "UART3"},
8.103 + {"uart4", Clock_uart4, "UART4"},
8.104 + {NULL, Clock_undefined, NULL},
8.105 };
8.106
8.107
9.1 --- a/pkg/landfall-examples/hw_info/x1600.c Thu Nov 16 17:48:32 2023 +0100
9.2 +++ b/pkg/landfall-examples/hw_info/x1600.c Thu Nov 16 22:03:51 2023 +0100
9.3 @@ -341,6 +341,16 @@
9.4 x1600_rtc_enable(rtc);
9.5 }
9.6
9.7 +void rtc_alarm_disable(void *rtc)
9.8 +{
9.9 + x1600_rtc_alarm_disable(rtc);
9.10 +}
9.11 +
9.12 +void rtc_alarm_enable(void *rtc)
9.13 +{
9.14 + x1600_rtc_alarm_enable(rtc);
9.15 +}
9.16 +
9.17 uint32_t rtc_get_seconds(void *rtc)
9.18 {
9.19 return x1600_rtc_get_seconds(rtc);
9.20 @@ -465,33 +475,36 @@
9.21 /* CPM definitions. */
9.22
9.23 struct clock_info clocks[] = {
9.24 - {"ext", Clock_external, "External"},
9.25 - {"plla", Clock_pll_A, "PLL A"},
9.26 - {"plle", Clock_pll_E, "PLL E"},
9.27 - {"pllm", Clock_pll_M, "PLL M"},
9.28 - {"main", Clock_main, "Main"},
9.29 - {"cpu", Clock_cpu, "CPU"},
9.30 - {"ahb0", Clock_hclock0, "AHB0"},
9.31 - {"ahb2", Clock_hclock2, "AHB2"},
9.32 - {"apb", Clock_pclock, "APB"},
9.33 - {"aic", Clock_aic, "AIC"},
9.34 - {"dma", Clock_dma, "DMA"},
9.35 - {"lcd0", Clock_lcd_pixel0, "LCD pixel"},
9.36 - {"msc0", Clock_msc0, "MSC0"},
9.37 - {"msc1", Clock_msc1, "MSC1"},
9.38 - {"otg", Clock_otg0, "USB OTG"},
9.39 - {"i2c0", Clock_i2c0, "I2C0"},
9.40 - {"i2c1", Clock_i2c1, "I2C1"},
9.41 - {"i2s0", Clock_i2s0, "I2S0"},
9.42 - {"i2s1", Clock_i2s1, "I2S1"},
9.43 - {"i2s0r", Clock_i2s0_rx, "I2S0 RX"},
9.44 - {"i2s0t", Clock_i2s0_tx, "I2S0 TX"},
9.45 - {"ssi0", Clock_ssi0, "SSI"},
9.46 - {"uart0", Clock_uart0, "UART0"},
9.47 - {"uart1", Clock_uart1, "UART1"},
9.48 - {"uart2", Clock_uart2, "UART2"},
9.49 - {"uart3", Clock_uart3, "UART3"},
9.50 - {NULL, Clock_undefined, NULL},
9.51 + {"ext", Clock_external, "EXCLK"},
9.52 + {"ext_512", Clock_external_div_512, "EXCLK/512"},
9.53 + {"rtc_ext", Clock_rtc_external, "RTCLK"},
9.54 + {"plla", Clock_pll_A, "PLL A"},
9.55 + {"plle", Clock_pll_E, "PLL E"},
9.56 + {"pllm", Clock_pll_M, "PLL M"},
9.57 + {"main", Clock_main, "Main (SCLK_A)"},
9.58 + {"cpu", Clock_cpu, "CPU"},
9.59 + {"ahb0", Clock_hclock0, "AHB0"},
9.60 + {"ahb2", Clock_hclock2, "AHB2"},
9.61 + {"apb", Clock_pclock, "APB"},
9.62 + {"aic", Clock_aic, "AIC"},
9.63 + {"dma", Clock_dma, "DMA"},
9.64 + {"lcd0", Clock_lcd_pixel0, "LCD pixel"},
9.65 + {"msc0", Clock_msc0, "MSC0"},
9.66 + {"msc1", Clock_msc1, "MSC1"},
9.67 + {"otg", Clock_otg0, "USB OTG"},
9.68 + {"i2c0", Clock_i2c0, "I2C0"},
9.69 + {"i2c1", Clock_i2c1, "I2C1"},
9.70 + {"i2s0", Clock_i2s0, "I2S0"},
9.71 + {"i2s1", Clock_i2s1, "I2S1"},
9.72 + {"i2s0r", Clock_i2s0_rx, "I2S0 RX"},
9.73 + {"i2s0t", Clock_i2s0_tx, "I2S0 TX"},
9.74 + {"rtc", Clock_rtc, "RTC"},
9.75 + {"ssi0", Clock_ssi0, "SSI"},
9.76 + {"uart0", Clock_uart0, "UART0"},
9.77 + {"uart1", Clock_uart1, "UART1"},
9.78 + {"uart2", Clock_uart2, "UART2"},
9.79 + {"uart3", Clock_uart3, "UART3"},
9.80 + {NULL, Clock_undefined, NULL},
9.81 };
9.82
9.83