1.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Fri May 17 16:32:55 2024 +0200
1.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Fri May 17 16:34:29 2024 +0200
1.3 @@ -296,9 +296,9 @@
1.4
1.5 clock_i2c1((Source(mux_pclock)), (Control(Clock_gate_i2c1))),
1.6
1.7 - clock_i2s0(Source(mux_i2s, Clock_source_i2s0), Control(Clock_gate_i2s0)),
1.8 + clock_i2s0_rx((Source(mux_i2s0_rx)), (Control(Clock_gate_i2s0_rx))),
1.9
1.10 - clock_i2s1(Source(mux_i2s, Clock_source_i2s1), Control(Clock_gate_i2s1)),
1.11 + clock_i2s0_tx((Source(mux_i2s0_tx)), (Control(Clock_gate_i2s0_tx))),
1.12
1.13 clock_main(Source(mux_main, Clock_source_main), Control(Clock_gate_main)),
1.14
1.15 @@ -413,17 +413,17 @@
1.16 clock_external_div((Source(mux_external)), (Divider_fixed(512)));
1.17
1.18 static Clock_divided_i2s
1.19 - clock_i2s0_rx(Source(mux_i2s0_rx),
1.20 - Control(Clock_gate_i2s0_rx),
1.21 - Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.22 - Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
1.23 - Clock_divider_i2s0_d_auto)),
1.24 + clock_i2s0(Source(mux_i2s, Clock_source_i2s0),
1.25 + Control(Clock_gate_i2s0),
1.26 + Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
1.27 + Clock_divider_i2s0_d, Clock_divider_i2s0_n_auto,
1.28 + Clock_divider_i2s0_d_auto)),
1.29
1.30 - clock_i2s0_tx(Source(mux_i2s0_tx),
1.31 - Control(Clock_gate_i2s0_tx),
1.32 - Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.33 - Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
1.34 - Clock_divider_i2s1_d_auto));
1.35 + clock_i2s1(Source(mux_i2s, Clock_source_i2s1),
1.36 + Control(Clock_gate_i2s1),
1.37 + Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
1.38 + Clock_divider_i2s1_d, Clock_divider_i2s1_n_auto,
1.39 + Clock_divider_i2s1_d_auto));
1.40
1.41 const double x1600_pll_intermediate_min = 600000000,
1.42 x1600_pll_intermediate_max = 2400000000;