3.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 01:38:13 2023 +0200
3.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Thu Sep 14 18:51:41 2023 +0200
3.3 @@ -263,42 +263,6 @@
3.4
3.5
3.6
3.7 -// Clock input descriptions.
3.8 -
3.9 -struct Clock_input_desc
3.10 -{
3.11 - uint32_t source_reg;
3.12 - enum Clock_source_bits source_bit;
3.13 - int num_inputs;
3.14 - enum Clock_input_identifiers inputs[3];
3.15 -};
3.16 -
3.17 -struct Clock_input_desc clock_input_desc[Clock_input_identifier_count] = {
3.18 -
3.19 - /* Clock_input_ahb2_apb */ {Clock_control, Clock_source_hclock2,
3.20 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M}},
3.21 -
3.22 - /* Clock_input_external */ {Reg_undefined, Clock_source_undefined,
3.23 - 0, {}},
3.24 -
3.25 - /* Clock_input_main */ {Clock_control, Clock_source_main,
3.26 - 3, {Clock_input_none, Clock_input_external, Clock_input_pll_A}},
3.27 -
3.28 - /* Clock_input_none */ {Reg_undefined, Clock_source_undefined,
3.29 - 0, {}},
3.30 -
3.31 - /* Clock_input_pll_A */ {Reg_undefined, Clock_source_undefined,
3.32 - 1, {Clock_input_external}},
3.33 -
3.34 - /* Clock_input_pll_E */ {Reg_undefined, Clock_source_undefined,
3.35 - 1, {Clock_input_external}},
3.36 -
3.37 - /* Clock_input_pll_M */ {Reg_undefined, Clock_source_undefined,
3.38 - 1, {Clock_input_external}},
3.39 -};
3.40 -
3.41 -
3.42 -
3.43 // Clock descriptions.
3.44
3.45 struct Clock_desc
3.46 @@ -315,8 +279,7 @@
3.47 enum Clock_divider_bits divider_bit;
3.48 uint32_t divider_mask;
3.49 int num_inputs;
3.50 - enum Clock_input_identifiers inputs[4];
3.51 - enum Clock_identifiers clock_input;
3.52 + enum Clock_identifiers inputs[4];
3.53 };
3.54
3.55 #define Clock_desc_undefined {Reg_undefined, Clock_source_undefined, \
3.56 @@ -324,11 +287,17 @@
3.57 Reg_undefined, Clock_change_enable_undefined, \
3.58 Reg_undefined, Clock_busy_undefined, \
3.59 Reg_undefined, Clock_divider_undefined, 0, \
3.60 - 0, {}, \
3.61 - Clock_undefined}
3.62 + 0, {}}
3.63
3.64 static struct Clock_desc clock_desc[Clock_identifier_count] = {
3.65
3.66 + /* Clock_ahb2_apb */ {Clock_control, Clock_source_hclock2,
3.67 + Reg_undefined, Clock_gate_undefined,
3.68 + Reg_undefined, Clock_change_enable_undefined,
3.69 + Reg_undefined, Clock_busy_undefined,
3.70 + Reg_undefined, Clock_divider_undefined, 0,
3.71 + 3, {Clock_none, Clock_main, Clock_pll_M}},
3.72 +
3.73 /* Clock_aic_bitclk */ Clock_desc_undefined,
3.74
3.75 /* Clock_aic_pclk */ Clock_desc_undefined,
3.76 @@ -338,74 +307,72 @@
3.77 Can_divider0, Clock_change_enable_can0,
3.78 Can_divider0, Clock_busy_can0,
3.79 Can_divider0, Clock_divider_can0, 0xff,
3.80 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
3.81 - Clock_undefined},
3.82 + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}},
3.83
3.84 /* Clock_can1 */ {Can_divider1, Clock_source_can1,
3.85 Clock_gate1, Clock_gate_can1,
3.86 Can_divider1, Clock_change_enable_can1,
3.87 Can_divider1, Clock_busy_can1,
3.88 Can_divider1, Clock_divider_can1, 0xff,
3.89 - 4, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E, Clock_input_external},
3.90 - Clock_undefined},
3.91 + 4, {Clock_main, Clock_pll_M, Clock_pll_E, Clock_external}},
3.92
3.93 /* Clock_cdbus */ {Cdbus_divider, Clock_source_cdbus,
3.94 Clock_gate1, Clock_gate_cdbus,
3.95 Cdbus_divider, Clock_change_enable_cdbus,
3.96 Cdbus_divider, Clock_busy_cdbus,
3.97 Cdbus_divider, Clock_divider_cdbus, 0xff,
3.98 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.99 - Clock_undefined},
3.100 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.101
3.102 /* Clock_cim */ {Cim_divider, Clock_source_cim,
3.103 Clock_gate0, Clock_gate_cim,
3.104 Cim_divider, Clock_change_enable_cim,
3.105 Cim_divider, Clock_busy_cim,
3.106 Cim_divider, Clock_divider_cim, 0xff,
3.107 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.108 - Clock_undefined},
3.109 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.110
3.111 /* Clock_cpu */ {Clock_control, Clock_source_cpu,
3.112 Reg_undefined, Clock_gate_undefined,
3.113 Clock_control, Clock_change_enable_cpu,
3.114 Clock_status, Clock_busy_cpu,
3.115 Clock_control, Clock_divider_cpu, 0x0f,
3.116 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
3.117 - Clock_undefined},
3.118 + 3, {Clock_none, Clock_main, Clock_pll_M}},
3.119
3.120 /* Clock_ddr */ {Ddr_divider, Clock_source_ddr,
3.121 Clock_gate0, Clock_gate_ddr,
3.122 Ddr_divider, Clock_change_enable_ddr,
3.123 Ddr_divider, Clock_busy_ddr,
3.124 Ddr_divider, Clock_divider_ddr, 0x0f,
3.125 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
3.126 - Clock_undefined},
3.127 + 3, {Clock_none, Clock_main, Clock_pll_M}},
3.128
3.129 /* Clock_dma */ {Reg_undefined, Clock_source_undefined,
3.130 Clock_gate0, Clock_gate_dma,
3.131 Reg_undefined, Clock_change_enable_undefined,
3.132 Reg_undefined, Clock_busy_undefined,
3.133 Reg_undefined, Clock_divider_undefined, 0,
3.134 - 0, {},
3.135 - Clock_pclock},
3.136 + 1, {Clock_pclock}},
3.137
3.138 /* Clock_emac */ Clock_desc_undefined,
3.139
3.140 + /* Clock_external */ {Reg_undefined, Clock_source_undefined,
3.141 + Reg_undefined, Clock_gate_undefined,
3.142 + Reg_undefined, Clock_change_enable_undefined,
3.143 + Reg_undefined, Clock_busy_undefined,
3.144 + Reg_undefined, Clock_divider_undefined, 0,
3.145 + 0, {}},
3.146 +
3.147 /* Clock_hclock0 */ {Clock_control, Clock_source_hclock0,
3.148 Clock_gate0, Clock_gate_ahb0,
3.149 Clock_control, Clock_change_enable_ahb0,
3.150 Reg_undefined, Clock_busy_undefined,
3.151 Clock_control, Clock_divider_hclock0, 0x0f,
3.152 - 3, {Clock_input_none, Clock_input_main, Clock_input_pll_M},
3.153 - Clock_undefined},
3.154 + 3, {Clock_none, Clock_main, Clock_pll_M}},
3.155
3.156 /* Clock_hclock2 */ {Reg_undefined, Clock_source_undefined,
3.157 Clock_gate0, Clock_gate_apb0,
3.158 Clock_control, Clock_change_enable_ahb2,
3.159 Reg_undefined, Clock_busy_undefined,
3.160 Clock_control, Clock_divider_hclock2, 0x0f,
3.161 - 1, {Clock_input_ahb2_apb},
3.162 - Clock_undefined},
3.163 + 1, {Clock_ahb2_apb}},
3.164
3.165 /* Clock_hdmi */ Clock_desc_undefined,
3.166
3.167 @@ -414,24 +381,21 @@
3.168 Reg_undefined, Clock_change_enable_undefined,
3.169 Reg_undefined, Clock_busy_undefined,
3.170 Reg_undefined, Clock_divider_undefined, 0,
3.171 - 0, {},
3.172 - Clock_pclock},
3.173 + 1, {Clock_pclock}},
3.174
3.175 /* Clock_i2c0 */ {Reg_undefined, Clock_source_undefined,
3.176 Clock_gate0, Clock_gate_i2c0,
3.177 Reg_undefined, Clock_change_enable_undefined,
3.178 Reg_undefined, Clock_busy_undefined,
3.179 Reg_undefined, Clock_divider_undefined, 0,
3.180 - 0, {},
3.181 - Clock_pclock},
3.182 + 1, {Clock_pclock}},
3.183
3.184 /* Clock_i2c1 */ {Reg_undefined, Clock_source_undefined,
3.185 Clock_gate0, Clock_gate_i2c1,
3.186 Reg_undefined, Clock_change_enable_undefined,
3.187 Reg_undefined, Clock_busy_undefined,
3.188 Reg_undefined, Clock_divider_undefined, 0,
3.189 - 0, {},
3.190 - Clock_pclock},
3.191 + 1, {Clock_pclock}},
3.192
3.193 /* Clock_i2s */ Clock_desc_undefined,
3.194
3.195 @@ -440,16 +404,14 @@
3.196 I2s_divider0, Clock_change_enable_i2s,
3.197 Reg_undefined, Clock_busy_undefined,
3.198 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
3.199 - 2, {Clock_input_main, Clock_input_pll_E},
3.200 - Clock_undefined},
3.201 + 2, {Clock_main, Clock_pll_E}},
3.202
3.203 /* Clock_i2s0_tx */ {I2s_divider0, Clock_source_i2s,
3.204 Clock_gate1, Clock_gate_i2s0_tx,
3.205 I2s_divider0, Clock_change_enable_i2s,
3.206 Reg_undefined, Clock_busy_undefined,
3.207 Reg_undefined, Clock_divider_undefined, 0, // NOTE: To define.
3.208 - 2, {Clock_input_main, Clock_input_pll_E},
3.209 - Clock_undefined},
3.210 + 2, {Clock_main, Clock_pll_E}},
3.211
3.212 /* Clock_kbc */ Clock_desc_undefined,
3.213
3.214 @@ -460,72 +422,91 @@
3.215 Lcd_divider, Clock_change_enable_lcd,
3.216 Lcd_divider, Clock_busy_lcd,
3.217 Lcd_divider, Clock_divider_lcd, 0xff,
3.218 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.219 - Clock_undefined},
3.220 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.221
3.222 /* Clock_mac */ {Mac_divider, Clock_source_mac,
3.223 Clock_gate1, Clock_gate_gmac0,
3.224 Mac_divider, Clock_change_enable_mac,
3.225 Mac_divider, Clock_busy_mac,
3.226 Mac_divider, Clock_divider_mac, 0xff,
3.227 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.228 - Clock_undefined},
3.229 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.230
3.231 - /* Clock_main */ {Reg_undefined, Clock_source_undefined,
3.232 + /* Clock_main */ {Clock_control, Clock_source_main,
3.233 Clock_control, Clock_gate_main,
3.234 Reg_undefined, Clock_change_enable_undefined,
3.235 Reg_undefined, Clock_busy_undefined,
3.236 Reg_undefined, Clock_divider_undefined, 0,
3.237 - 1, {Clock_input_main},
3.238 - Clock_undefined},
3.239 + 3, {Clock_none, Clock_external, Clock_pll_A}},
3.240
3.241 /* Clock_msc */ {Msc_divider0, Clock_source_msc0,
3.242 Clock_gate0, Clock_gate_msc0,
3.243 Msc_divider0, Clock_change_enable_msc0,
3.244 Msc_divider0, Clock_busy_msc0,
3.245 Msc_divider0, Clock_divider_msc0, 0xff,
3.246 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.247 - Clock_undefined},
3.248 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.249
3.250 /* Clock_msc0 */ {Msc_divider0, Clock_source_msc0,
3.251 Clock_gate0, Clock_gate_msc0,
3.252 Msc_divider0, Clock_change_enable_msc0,
3.253 Msc_divider0, Clock_busy_msc0,
3.254 Msc_divider0, Clock_divider_msc0, 0xff,
3.255 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.256 - Clock_undefined},
3.257 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.258
3.259 /* Clock_msc1 */ {Msc_divider1, Clock_source_msc1,
3.260 Clock_gate0, Clock_gate_msc1,
3.261 Msc_divider1, Clock_change_enable_msc1,
3.262 Msc_divider1, Clock_busy_msc1,
3.263 Msc_divider1, Clock_divider_msc1, 0xff,
3.264 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.265 - Clock_undefined},
3.266 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.267 +
3.268 + /* Clock_none */ {Reg_undefined, Clock_source_undefined,
3.269 + Reg_undefined, Clock_gate_undefined,
3.270 + Reg_undefined, Clock_change_enable_undefined,
3.271 + Reg_undefined, Clock_busy_undefined,
3.272 + Reg_undefined, Clock_divider_undefined, 0,
3.273 + 0, {}},
3.274
3.275 /* Clock_pclock */ {Reg_undefined, Clock_source_undefined,
3.276 Clock_gate0, Clock_gate_apb0,
3.277 Reg_undefined, Clock_change_enable_undefined,
3.278 Reg_undefined, Clock_busy_undefined,
3.279 Clock_control, Clock_divider_pclock, 0x0f,
3.280 - 1, {Clock_input_ahb2_apb},
3.281 - Clock_undefined},
3.282 + 1, {Clock_ahb2_apb}},
3.283 +
3.284 + /* Clock_pll_A */ {Reg_undefined, Clock_source_undefined,
3.285 + Reg_undefined, Clock_gate_undefined,
3.286 + Reg_undefined, Clock_change_enable_undefined,
3.287 + Reg_undefined, Clock_busy_undefined,
3.288 + Reg_undefined, Clock_divider_undefined, 0,
3.289 + 1, {Clock_external}},
3.290 +
3.291 + /* Clock_pll_E */ {Reg_undefined, Clock_source_undefined,
3.292 + Reg_undefined, Clock_gate_undefined,
3.293 + Reg_undefined, Clock_change_enable_undefined,
3.294 + Reg_undefined, Clock_busy_undefined,
3.295 + Reg_undefined, Clock_divider_undefined, 0,
3.296 + 1, {Clock_external}},
3.297 +
3.298 + /* Clock_pll_M */ {Reg_undefined, Clock_source_undefined,
3.299 + Reg_undefined, Clock_gate_undefined,
3.300 + Reg_undefined, Clock_change_enable_undefined,
3.301 + Reg_undefined, Clock_busy_undefined,
3.302 + Reg_undefined, Clock_divider_undefined, 0,
3.303 + 1, {Clock_external}},
3.304
3.305 /* Clock_pwm */ {Pwm_divider, Clock_source_pwm,
3.306 Clock_gate1, Clock_gate_pwm,
3.307 Pwm_divider, Clock_change_enable_pwm,
3.308 Pwm_divider, Clock_busy_pwm,
3.309 Pwm_divider, Clock_divider_pwm, 0x0f,
3.310 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.311 - Clock_undefined},
3.312 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.313
3.314 /* Clock_pwm0 */ {Pwm_divider, Clock_source_pwm,
3.315 Clock_gate1, Clock_gate_pwm,
3.316 Pwm_divider, Clock_change_enable_pwm,
3.317 Pwm_divider, Clock_busy_pwm,
3.318 Pwm_divider, Clock_divider_pwm, 0x0f,
3.319 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.320 - Clock_undefined},
3.321 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.322
3.323 /* Clock_pwm1 */ Clock_desc_undefined,
3.324
3.325 @@ -536,8 +517,7 @@
3.326 Sfc_divider, Clock_change_enable_sfc,
3.327 Sfc_divider, Clock_busy_sfc,
3.328 Sfc_divider, Clock_divider_sfc, 0xff,
3.329 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.330 - Clock_undefined},
3.331 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.332
3.333 /* Clock_smb0 */ Clock_desc_undefined,
3.334
3.335 @@ -554,48 +534,42 @@
3.336 Ssi_divider, Clock_change_enable_ssi,
3.337 Ssi_divider, Clock_busy_ssi,
3.338 Ssi_divider, Clock_divider_ssi, 0xff,
3.339 - 3, {Clock_input_main, Clock_input_pll_M, Clock_input_pll_E},
3.340 - Clock_undefined},
3.341 + 3, {Clock_main, Clock_pll_M, Clock_pll_E}},
3.342
3.343 /* Clock_timer */ {Reg_undefined, Clock_source_undefined,
3.344 Clock_gate0, Clock_gate_timer,
3.345 Reg_undefined, Clock_change_enable_undefined,
3.346 Reg_undefined, Clock_busy_undefined,
3.347 Reg_undefined, Clock_divider_undefined, 0,
3.348 - 0, {},
3.349 - Clock_pclock},
3.350 + 1, {Clock_pclock}},
3.351
3.352 /* Clock_uart0 */ {Reg_undefined, Clock_source_undefined,
3.353 Clock_gate0, Clock_gate_uart0,
3.354 Reg_undefined, Clock_change_enable_undefined,
3.355 Reg_undefined, Clock_busy_undefined,
3.356 Reg_undefined, Clock_divider_undefined, 0,
3.357 - 1, {Clock_input_external},
3.358 - Clock_undefined},
3.359 + 1, {Clock_external}},
3.360
3.361 /* Clock_uart1 */ {Reg_undefined, Clock_source_undefined,
3.362 Clock_gate0, Clock_gate_uart1,
3.363 Reg_undefined, Clock_change_enable_undefined,
3.364 Reg_undefined, Clock_busy_undefined,
3.365 Reg_undefined, Clock_divider_undefined, 0,
3.366 - 1, {Clock_input_external},
3.367 - Clock_undefined},
3.368 + 1, {Clock_external}},
3.369
3.370 /* Clock_uart2 */ {Reg_undefined, Clock_source_undefined,
3.371 Clock_gate0, Clock_gate_uart2,
3.372 Reg_undefined, Clock_change_enable_undefined,
3.373 Reg_undefined, Clock_busy_undefined,
3.374 Reg_undefined, Clock_divider_undefined, 0,
3.375 - 1, {Clock_input_external},
3.376 - Clock_undefined},
3.377 + 1, {Clock_external}},
3.378
3.379 /* Clock_uart3 */ {Reg_undefined, Clock_source_undefined,
3.380 Clock_gate1, Clock_gate_uart3,
3.381 Reg_undefined, Clock_change_enable_undefined,
3.382 Reg_undefined, Clock_busy_undefined,
3.383 Reg_undefined, Clock_divider_undefined, 0,
3.384 - 1, {Clock_input_external},
3.385 - Clock_undefined},
3.386 + 1, {Clock_external}},
3.387
3.388 /* Clock_udc */ Clock_desc_undefined,
3.389
3.390 @@ -892,68 +866,32 @@
3.391 // Clock source frequencies.
3.392
3.393 uint32_t
3.394 -Cpm_x1600_chip::get_input_frequency(enum Clock_input_identifiers clock)
3.395 -{
3.396 - struct Clock_input_desc desc = clock_input_desc[clock];
3.397 -
3.398 - // Clocks with no inputs provide a frequency.
3.399 -
3.400 - if (desc.num_inputs == 0)
3.401 - {
3.402 - switch (clock)
3.403 - {
3.404 - case Clock_input_external: return _exclk_freq;
3.405 - default: return 0;
3.406 - }
3.407 - }
3.408 -
3.409 - // Of the input clocks, only PLLs have a single input.
3.410 -
3.411 - else if (desc.num_inputs == 1)
3.412 - {
3.413 - switch (clock)
3.414 - {
3.415 - case Clock_input_pll_A: return get_pll_frequency(Pll_control_A);
3.416 - case Clock_input_pll_E: return get_pll_frequency(Pll_control_E);
3.417 - case Clock_input_pll_M: return get_pll_frequency(Pll_control_M);
3.418 - default: return 0;
3.419 - }
3.420 - }
3.421 -
3.422 - // With multiple sources, obtain the selected source for the clock.
3.423 -
3.424 - uint8_t source = get_field(desc.source_reg, Source_mask, desc.source_bit);
3.425 -
3.426 - // Return the frequency of the source.
3.427 -
3.428 - if (source < desc.num_inputs)
3.429 - return get_input_frequency(desc.inputs[source]);
3.430 - else
3.431 - return 0;
3.432 -}
3.433 -
3.434 -uint32_t
3.435 Cpm_x1600_chip::get_source_frequency(enum Clock_identifiers clock)
3.436 {
3.437 struct Clock_desc desc = clock_desc[clock];
3.438
3.439 if (desc.num_inputs == 0)
3.440 {
3.441 - // Clocks may reference other clocks.
3.442 -
3.443 - if (desc.clock_input != Clock_undefined)
3.444 - return get_frequency(desc.clock_input);
3.445 -
3.446 - // Undefined clocks return zero.
3.447 -
3.448 - else
3.449 - return 0;
3.450 + switch (clock)
3.451 + {
3.452 + case Clock_external: return _exclk_freq;
3.453 + default: return 0;
3.454 + }
3.455 }
3.456
3.457 - // Clocks with one source yield that input frequency.
3.458 + // Clocks with one source yield that input frequency, although PLLs are
3.459 + // handled specially.
3.460
3.461 else if (desc.num_inputs == 1)
3.462 - return get_input_frequency(desc.inputs[0]);
3.463 + {
3.464 + switch (clock)
3.465 + {
3.466 + case Clock_pll_A: return get_pll_frequency(Pll_control_A);
3.467 + case Clock_pll_E: return get_pll_frequency(Pll_control_E);
3.468 + case Clock_pll_M: return get_pll_frequency(Pll_control_M);
3.469 + default: return get_frequency(desc.inputs[0]);
3.470 + }
3.471 + }
3.472
3.473 // With multiple sources, obtain the selected source for the clock.
3.474
3.475 @@ -962,7 +900,7 @@
3.476 // Return the frequency of the source.
3.477
3.478 if (source < desc.num_inputs)
3.479 - return get_input_frequency(desc.inputs[source]);
3.480 + return get_frequency(desc.inputs[source]);
3.481 else
3.482 return 0;
3.483 }