3.1 --- a/pkg/devices/lib/cpm/src/x1600.cc Sun Sep 17 18:41:41 2023 +0200
3.2 +++ b/pkg/devices/lib/cpm/src/x1600.cc Sun Sep 17 19:16:38 2023 +0200
3.3 @@ -236,147 +236,141 @@
3.4
3.5 #define Clocks(...) ((enum Clock_identifiers []) {__VA_ARGS__})
3.6
3.7 -Mux mux_external(Clock_external);
3.8 -
3.9 -Mux mux_pclock(Clock_pclock);
3.10 -
3.11 -Mux mux_ahb2_apb(Clock_ahb2_apb);
3.12 -
3.13 -Mux mux_core(3, Clocks(Clock_none, Clock_main, Clock_pll_M));
3.14 -
3.15 -Mux mux_bus(4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external));
3.16 -
3.17 -Mux mux_dev(3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E));
3.18 -
3.19 -Mux mux_i2s(2, Clocks(Clock_main, Clock_pll_E));
3.20 +static Mux mux_external (Clock_external),
3.21 + mux_pclock (Clock_pclock),
3.22 + mux_ahb2_apb (Clock_ahb2_apb),
3.23 + mux_core (3, Clocks(Clock_none, Clock_main, Clock_pll_M)),
3.24 + mux_bus (4, Clocks(Clock_main, Clock_pll_M, Clock_pll_E, Clock_external)),
3.25 + mux_dev (3, Clocks(Clock_main, Clock_pll_M, Clock_pll_E)),
3.26 + mux_i2s (2, Clocks(Clock_main, Clock_pll_E));
3.27
3.28
3.29
3.30 // Clock instances.
3.31
3.32 -Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2));
3.33 -
3.34 -Clock clock_can0(Source(mux_bus, Clock_source_can0),
3.35 - Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
3.36 - Divider(Clock_divider_can0));
3.37 -
3.38 -Clock clock_can1(Source(mux_bus, Clock_source_can1),
3.39 - Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
3.40 - Divider(Clock_divider_can1));
3.41 -
3.42 -Clock clock_cdbus(Source(mux_dev, Clock_source_cdbus),
3.43 - Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
3.44 - Divider(Clock_divider_cdbus));
3.45 -
3.46 -Clock clock_cim(Source(mux_dev, Clock_source_cim),
3.47 - Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
3.48 - Divider(Clock_divider_cim));
3.49 -
3.50 -Clock clock_cpu(Source(mux_core, Clock_source_cpu),
3.51 - Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
3.52 - Divider(Clock_divider_cpu));
3.53 -
3.54 -Clock clock_ddr(Source(mux_core, Clock_source_ddr),
3.55 - Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
3.56 - Divider(Clock_divider_ddr));
3.57 -
3.58 -Clock clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined);
3.59 -
3.60 -Clock_passive clock_external;
3.61 +static Clock_passive clock_external;
3.62
3.63 -Clock clock_hclock0(Source(mux_core, Clock_source_hclock0),
3.64 - Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
3.65 - Divider(Clock_divider_hclock0));
3.66 -
3.67 -Clock clock_hclock2(Source(mux_ahb2_apb),
3.68 - Control(Clock_gate_apb0, Clock_change_enable_ahb2),
3.69 - Divider(Clock_divider_hclock2));
3.70 -
3.71 -Clock clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined);
3.72 -
3.73 -Clock clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined);
3.74 -
3.75 -Clock clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined);
3.76 +static Clock_null clock_none;
3.77
3.78 -Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
3.79 - Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
3.80 - Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
3.81 - Clock_divider_i2s0_d));
3.82 -
3.83 -Clock_divided_i2s clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
3.84 - Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
3.85 - Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
3.86 - Clock_divider_i2s1_d));
3.87 -
3.88 -Clock clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
3.89 - Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
3.90 - Divider(Clock_divider_lcd));
3.91 -
3.92 -Clock clock_mac(Source(mux_dev, Clock_source_mac),
3.93 - Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
3.94 - Divider(Clock_divider_mac));
3.95 +static Clock clock_ahb2_apb(Source(mux_core, Clock_source_hclock2)),
3.96
3.97 -Clock clock_main(Source(mux_core, Clock_source_main),
3.98 - Control(Clock_gate_main));
3.99 -
3.100 -Clock clock_msc(Source(mux_dev, Clock_source_msc0),
3.101 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.102 - Divider(Clock_divider_msc0));
3.103 -
3.104 -Clock clock_msc0(Source(mux_dev, Clock_source_msc0),
3.105 - Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.106 - Divider(Clock_divider_msc0));
3.107 -
3.108 -Clock clock_msc1(Source(mux_dev, Clock_source_msc1),
3.109 - Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
3.110 - Divider(Clock_divider_msc1));
3.111 -
3.112 -Clock_null clock_none;
3.113 -
3.114 -Clock clock_pclock(Source(mux_ahb2_apb),
3.115 - Control(Clock_gate_apb0, Field::undefined, Field::undefined),
3.116 - Divider(Clock_divider_pclock));
3.117 -
3.118 -Pll clock_pll_A(Source(mux_external),
3.119 - Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
3.120 - Divider_pll(Pll_multiplier_A, Pll_input_division_A,
3.121 - Pll_output_division0_A, Pll_output_division1_A));
3.122 -
3.123 -Pll clock_pll_E(Source(mux_external),
3.124 - Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
3.125 - Divider_pll(Pll_multiplier_E, Pll_input_division_E,
3.126 - Pll_output_division0_E, Pll_output_division1_E));
3.127 + clock_can0(Source(mux_bus, Clock_source_can0),
3.128 + Control(Clock_gate_can0, Clock_change_enable_can0, Clock_busy_can0),
3.129 + Divider(Clock_divider_can0)),
3.130 +
3.131 + clock_can1(Source(mux_bus, Clock_source_can1),
3.132 + Control(Clock_gate_can1, Clock_change_enable_can1, Clock_busy_can1),
3.133 + Divider(Clock_divider_can1)),
3.134 +
3.135 + clock_cdbus(Source(mux_dev, Clock_source_cdbus),
3.136 + Control(Clock_gate_cdbus, Clock_change_enable_cdbus, Clock_busy_cdbus),
3.137 + Divider(Clock_divider_cdbus)),
3.138 +
3.139 + clock_cim(Source(mux_dev, Clock_source_cim),
3.140 + Control(Clock_gate_cim, Clock_change_enable_cim, Clock_busy_cim),
3.141 + Divider(Clock_divider_cim)),
3.142 +
3.143 + clock_cpu(Source(mux_core, Clock_source_cpu),
3.144 + Control(Field::undefined, Clock_change_enable_cpu, Clock_busy_cpu),
3.145 + Divider(Clock_divider_cpu)),
3.146 +
3.147 + clock_ddr(Source(mux_core, Clock_source_ddr),
3.148 + Control(Clock_gate_ddr, Clock_change_enable_ddr, Clock_busy_ddr),
3.149 + Divider(Clock_divider_ddr)),
3.150 +
3.151 + clock_dma(Source(mux_pclock), Control(Clock_gate_dma), Divider::undefined),
3.152 +
3.153 + clock_hclock0(Source(mux_core, Clock_source_hclock0),
3.154 + Control(Clock_gate_ahb0, Clock_change_enable_ahb0),
3.155 + Divider(Clock_divider_hclock0)),
3.156 +
3.157 + clock_hclock2(Source(mux_ahb2_apb),
3.158 + Control(Clock_gate_apb0, Clock_change_enable_ahb2),
3.159 + Divider(Clock_divider_hclock2)),
3.160 +
3.161 + clock_i2c(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
3.162 +
3.163 + clock_i2c0(Source(mux_pclock), Control(Clock_gate_i2c0), Divider::undefined),
3.164 +
3.165 + clock_i2c1(Source(mux_pclock), Control(Clock_gate_i2c1), Divider::undefined),
3.166 +
3.167 + clock_lcd_pixel(Source(mux_dev, Clock_source_lcd),
3.168 + Control(Clock_gate_lcd_pixel, Clock_change_enable_lcd, Clock_busy_lcd),
3.169 + Divider(Clock_divider_lcd)),
3.170 +
3.171 + clock_mac(Source(mux_dev, Clock_source_mac),
3.172 + Control(Clock_gate_gmac0, Clock_change_enable_mac, Clock_busy_mac),
3.173 + Divider(Clock_divider_mac)),
3.174 +
3.175 + clock_main(Source(mux_core, Clock_source_main),
3.176 + Control(Clock_gate_main)),
3.177 +
3.178 + clock_msc(Source(mux_dev, Clock_source_msc0),
3.179 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.180 + Divider(Clock_divider_msc0)),
3.181 +
3.182 + clock_msc0(Source(mux_dev, Clock_source_msc0),
3.183 + Control(Clock_gate_msc0, Clock_change_enable_msc0, Clock_busy_msc0),
3.184 + Divider(Clock_divider_msc0)),
3.185 +
3.186 + clock_msc1(Source(mux_dev, Clock_source_msc1),
3.187 + Control(Clock_gate_msc1, Clock_change_enable_msc1, Clock_busy_msc1),
3.188 + Divider(Clock_divider_msc1)),
3.189 +
3.190 + clock_pclock(Source(mux_ahb2_apb),
3.191 + Control(Clock_gate_apb0, Field::undefined, Field::undefined),
3.192 + Divider(Clock_divider_pclock)),
3.193 +
3.194 + clock_pwm(Source(mux_dev, Clock_source_pwm),
3.195 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.196 + Divider(Clock_divider_pwm)),
3.197 +
3.198 + clock_pwm0(Source(mux_dev, Clock_source_pwm),
3.199 + Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.200 + Divider(Clock_divider_pwm)),
3.201 +
3.202 + clock_sfc(Source(mux_dev, Clock_source_sfc),
3.203 + Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
3.204 + Divider(Clock_divider_sfc)),
3.205 +
3.206 + clock_ssi(Source(mux_dev, Clock_source_ssi),
3.207 + Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
3.208 + Divider(Clock_divider_ssi)),
3.209 +
3.210 + clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined),
3.211 +
3.212 + clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined),
3.213 +
3.214 + clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined),
3.215 +
3.216 + clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined),
3.217 +
3.218 + clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined);
3.219 +
3.220 +static Clock_divided_i2s clock_i2s0_rx(Source(mux_i2s, Clock_source_i2s),
3.221 + Control(Clock_gate_i2s0_rx, Clock_change_enable_i2s),
3.222 + Divider_i2s(Clock_divider_i2s0_m, Clock_divider_i2s0_n,
3.223 + Clock_divider_i2s0_d)),
3.224
3.225 -Pll clock_pll_M(Source(mux_external),
3.226 - Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
3.227 - Divider_pll(Pll_multiplier_M, Pll_input_division_M,
3.228 - Pll_output_division0_M, Pll_output_division1_M));
3.229 + clock_i2s0_tx(Source(mux_i2s, Clock_source_i2s),
3.230 + Control(Clock_gate_i2s0_tx, Clock_change_enable_i2s),
3.231 + Divider_i2s(Clock_divider_i2s1_m, Clock_divider_i2s1_n,
3.232 + Clock_divider_i2s1_d));
3.233
3.234 -Clock clock_pwm(Source(mux_dev, Clock_source_pwm),
3.235 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.236 - Divider(Clock_divider_pwm));
3.237 -
3.238 -Clock clock_pwm0(Source(mux_dev, Clock_source_pwm),
3.239 - Control(Clock_gate_pwm, Clock_change_enable_pwm, Clock_busy_pwm),
3.240 - Divider(Clock_divider_pwm));
3.241 +static Pll clock_pll_A(Source(mux_external),
3.242 + Control_pll(Pll_enable_A, Pll_stable_A, Pll_bypass_A),
3.243 + Divider_pll(Pll_multiplier_A, Pll_input_division_A,
3.244 + Pll_output_division0_A, Pll_output_division1_A)),
3.245
3.246 -Clock clock_sfc(Source(mux_dev, Clock_source_sfc),
3.247 - Control(Clock_gate_sfc, Clock_change_enable_sfc, Clock_busy_sfc),
3.248 - Divider(Clock_divider_sfc));
3.249 -
3.250 -Clock clock_ssi(Source(mux_dev, Clock_source_ssi),
3.251 - Control(Clock_gate_ssi0, Clock_change_enable_ssi, Clock_busy_ssi),
3.252 - Divider(Clock_divider_ssi));
3.253 + clock_pll_E(Source(mux_external),
3.254 + Control_pll(Pll_enable_E, Pll_stable_E, Pll_bypass_E),
3.255 + Divider_pll(Pll_multiplier_E, Pll_input_division_E,
3.256 + Pll_output_division0_E, Pll_output_division1_E)),
3.257
3.258 -Clock clock_timer(Source(mux_pclock), Control(Clock_gate_timer), Divider::undefined);
3.259 -
3.260 -Clock clock_uart0(Source(mux_external), Control(Clock_gate_uart0), Divider::undefined);
3.261 -
3.262 -Clock clock_uart1(Source(mux_external), Control(Clock_gate_uart1), Divider::undefined);
3.263 -
3.264 -Clock clock_uart2(Source(mux_external), Control(Clock_gate_uart2), Divider::undefined);
3.265 -
3.266 -Clock clock_uart3(Source(mux_external), Control(Clock_gate_uart3), Divider::undefined);
3.267 + clock_pll_M(Source(mux_external),
3.268 + Control_pll(Pll_enable_M, Pll_stable_M, Pll_bypass_M),
3.269 + Divider_pll(Pll_multiplier_M, Pll_input_division_M,
3.270 + Pll_output_division0_M, Pll_output_division1_M));
3.271
3.272
3.273
3.274 @@ -452,6 +446,12 @@
3.275 // register_property("exclk_freq", &exclk_freq);
3.276 }
3.277
3.278 +const char *
3.279 +Cpm_x1600_chip::clock_type(enum Clock_identifiers clock)
3.280 +{
3.281 + return clocks[clock]->clock_type();
3.282 +}
3.283 +
3.284 int
3.285 Cpm_x1600_chip::have_clock(enum Clock_identifiers clock)
3.286 {
3.287 @@ -580,6 +580,12 @@
3.288 return (void *) new Cpm_x1600_chip(cpm_base, 24000000);
3.289 }
3.290
3.291 +const char *
3.292 +x1600_cpm_clock_type(void *cpm, enum Clock_identifiers clock)
3.293 +{
3.294 + return static_cast<Cpm_x1600_chip *>(cpm)->clock_type(clock);
3.295 +}
3.296 +
3.297 int
3.298 x1600_cpm_have_clock(void *cpm, enum Clock_identifiers clock)
3.299 {