paul@22 | 1 | Timing
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paul@22 | 2 | ------
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paul@22 | 3 |
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paul@40 | 4 | According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
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paul@40 | 5 | of which are used to generate pixel data. At 50Hz, this means that 128 cycles
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paul@40 | 6 | are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
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paul@40 | 7 | 312 ~= 128 cycles). This is consistent with the observation that each scanline
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paul@37 | 8 | requires at most 80 bytes of data, and that the ULA is apparently busy for 40
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paul@37 | 9 | out of 64 microseconds in each scanline.
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paul@22 | 10 |
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paul@33 | 11 | Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
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paul@33 | 12 | each providing two bits of each byte) using two cycles within the 500ns period
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paul@36 | 13 | of the 2MHz clock to complete each access operation. Since the CPU and ULA
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paul@36 | 14 | have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
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paul@36 | 15 | effectively run at 1MHz (since every other 500ns period involves the ULA
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paul@36 | 16 | accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
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paul@36 | 17 | frequency is divided by the ULA (IC1) depending on the screen mode in use.
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paul@33 | 18 |
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paul@37 | 19 | Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
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paul@37 | 20 | patterns corresponding to 16MHz cycles are required:
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paul@37 | 21 |
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paul@39 | 22 | Time (ns): 0-------------- 500------------ ...
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paul@37 | 23 | 2 MHz cycle: 0 1 ...
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paul@37 | 24 | 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
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paul@39 | 25 | ~RAS: 0 1 0 1 ...
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paul@39 | 26 | ~CAS: 0 1 0 1 0 1 0 1 ...
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paul@39 | 27 | A B B A B B ...
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paul@39 | 28 | F S F S ...
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paul@39 | 29 | a b b a b b ...
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paul@37 | 30 |
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paul@37 | 31 | Here, "A" indicates the row and column addresses being latched into the RAM
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paul@38 | 32 | (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
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paul@37 | 33 | second column address being latched into the RAM. Presumably, the first and
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paul@39 | 34 | second half-bytes can be read at "F" and "S" respectively, and the row and
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paul@39 | 35 | column addresses must be made available at "a" and "b" respectively at the
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paul@39 | 36 | latest.
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paul@37 | 37 |
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paul@38 | 38 | Note that the Service Manual refers to the negative edge of RAS and CAS, but
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paul@38 | 39 | the datasheet for the similar TM4164EC4 product shows latching on the negative
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paul@38 | 40 | edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
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paul@38 | 41 | communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
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paul@38 | 42 | "page mode" provides the appropriate behaviour for that particular product.
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paul@38 | 43 |
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paul@40 | 44 | Video Timing
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paul@40 | 45 | ------------
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paul@40 | 46 |
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paul@40 | 47 | According to 8.7 in the Service Manual, and the PAL Wikipedia page,
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paul@40 | 48 | approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
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paul@40 | 49 | (including the "colour burst"), and 1.65µs for the "front porch", totalling
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paul@40 | 50 | 12.05µs and thus leaving 51.95µs for the active video signal for each
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paul@40 | 51 | scanline. As the Service Manual suggests in the oscilloscope traces, the
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paul@40 | 52 | display information is transmitted more or less centred within the active
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paul@40 | 53 | video period since the ULA will only be providing pixel data for 40µs in each
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paul@40 | 54 | scanline.
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paul@39 | 55 |
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paul@39 | 56 | Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
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paul@39 | 57 | each scanline can be divided into 1024 cycles, although only 640 at most are
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paul@40 | 58 | actively used to provide pixel data. Pixel data production should only occur
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paul@40 | 59 | within a certain period on each scanline, approximately 262 cycles after the
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paul@40 | 60 | start of hsync:
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paul@40 | 61 |
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paul@40 | 62 | active video period = 51.95µs
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paul@40 | 63 | pixel data period = 40µs
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paul@40 | 64 | total silent period = 51.95µs - 40µs = 11.95µs
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paul@40 | 65 | silent periods (before and after) = 11.95µs / 2 = 5.975µs
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paul@40 | 66 | hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
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paul@40 | 67 | time before pixel data period = 10.4µs + 5.975µs = 16.375µs
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paul@40 | 68 | pixel data period start cycle = 16.375µs / 62.5ns = 262
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paul@40 | 69 |
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paul@40 | 70 | By choosing a number divisible by 8, the RAM access mechanism can be
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paul@40 | 71 | synchronised with the pixel production. Thus, 264 is a more appropriate start
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paul@40 | 72 | cycle.
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paul@40 | 73 |
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paul@40 | 74 | The "vertical blanking period", meaning the period before picture information
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paul@40 | 75 | in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
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paul@40 | 76 | 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
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paul@40 | 77 | for 2.5 lines. Thus, the first visible scanline on the first field of a frame
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paul@40 | 78 | occurs half way through the 23rd scanline period measured from the start of
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paul@40 | 79 | vsync:
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paul@40 | 80 |
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paul@40 | 81 | 10 20 23
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paul@40 | 82 | Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
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paul@40 | 83 | Line from 1: 0 22 3
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paul@40 | 84 | Line on screen: .:::::VVVVV::::: 12233445566
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paul@40 | 85 | |_________________________________________________|
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paul@40 | 86 | 25 line vertical blanking period
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paul@40 | 87 |
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paul@40 | 88 | In the second field of a frame, the first visible scanline coincides with the
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paul@40 | 89 | 24th scanline period measured from the start of line 313 in the frame:
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paul@40 | 90 |
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paul@40 | 91 | 310 336
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paul@40 | 92 | Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
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paul@40 | 93 | Line from 313: 0 23
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paul@40 | 94 | Line on screen: 88:::::VVVVV:::: 11223344
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paul@40 | 95 | 288 | |
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paul@40 | 96 | |_________________________________________________|
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paul@40 | 97 | 25 line vertical blanking period
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paul@40 | 98 |
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paul@40 | 99 | In order to consider only full lines, we might consider the start of each
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paul@40 | 100 | frame to occur 23 lines after the start of vsync.
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paul@40 | 101 |
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paul@40 | 102 | Again, it is likely that pixel data production should only occur on scanlines
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paul@40 | 103 | within a certain period on each frame. The "625/50" document indicates that
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paul@40 | 104 | only a certain region is "safe" to use, suggesting a vertically centred region
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paul@40 | 105 | with approximately 15 blank lines above and below the picture. Thus, the start
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paul@40 | 106 | of the picture could be chosen as 38 lines after the start of vsync.
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paul@40 | 107 |
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paul@40 | 108 | See: Acorn Electron Advanced User Guide
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paul@40 | 109 | See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
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paul@40 | 110 | See: http://en.wikipedia.org/wiki/PAL
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paul@40 | 111 | See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
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paul@40 | 112 | See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
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paul@40 | 113 | http://lipas.uwasa.fi/~f76998/video/modes/
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paul@40 | 114 | See: PAL TV timing and voltages
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paul@40 | 115 | http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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paul@40 | 116 | See: Line Standards
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paul@40 | 117 | http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
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paul@40 | 118 | See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
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paul@40 | 119 | http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
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paul@40 | 120 | See: Acorn Electron Service Manual
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paul@40 | 121 | http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
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paul@39 | 122 |
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paul@43 | 123 | Interrupts
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paul@43 | 124 | ----------
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paul@43 | 125 |
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paul@43 | 126 | The ULA generates IRQs (maskable interrupts) according to certain conditions
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paul@43 | 127 | and these conditions are controlled by location &FE00:
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paul@43 | 128 |
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paul@43 | 129 | * Vertical sync (bottom of displayed screen)
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paul@43 | 130 | * 50MHz real time clock
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paul@43 | 131 | * Transmit data empty
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paul@43 | 132 | * Receive data full
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paul@43 | 133 | * High tone detect
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paul@43 | 134 |
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paul@43 | 135 | The ULA is also used to clear interrupt conditions through location &FE05. Of
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paul@43 | 136 | particular significance is bit 7, which must be set if an NMI (non-maskable
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paul@43 | 137 | interrupt) has occurred and has thus suspended ULA access to memory, restoring
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paul@43 | 138 | the normal function of the ULA.
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paul@43 | 139 |
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paul@43 | 140 | ROM Paging
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paul@43 | 141 | ----------
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paul@43 | 142 |
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paul@43 | 143 | Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
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paul@43 | 144 | mappings exist:
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paul@43 | 145 |
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paul@43 | 146 | 8 keyboard
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paul@43 | 147 | 9 keyboard (duplicate)
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paul@43 | 148 | 10 BASIC ROM
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paul@43 | 149 | 11 BASIC ROM (duplicate)
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paul@43 | 150 |
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paul@43 | 151 | Paging in a ROM involves the following procedure:
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paul@43 | 152 |
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paul@43 | 153 | 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
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paul@43 | 154 | 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
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paul@43 | 155 | selected.
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paul@43 | 156 | 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
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paul@43 | 157 | whilst writing the desired ROM number n in bits 0 to 2.
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paul@43 | 158 |
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paul@37 | 159 | Shadow/Expanded Memory
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paul@37 | 160 | ----------------------
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paul@37 | 161 |
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paul@37 | 162 | The Electron exposes all sixteen address lines and all eight data lines
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paul@37 | 163 | through the expansion bus. Using such lines, it is possible to provide
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paul@37 | 164 | additional memory - typically sideways ROM and RAM - on expansion cards and
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paul@37 | 165 | through cartridges, although the official cartridge specification provides
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paul@37 | 166 | fewer address lines and only seeks to provide access to memory in 16K units.
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paul@37 | 167 |
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paul@37 | 168 | Various modifications and upgrades were developed to offer "turbo"
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paul@37 | 169 | capabilities to the Electron, permitting the CPU to access a separate 8K of
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paul@37 | 170 | RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
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paul@37 | 171 | the ULA through additional logic. However, an enhanced ULA might support
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paul@37 | 172 | independent CPU access to memory over the expansion bus by allowing itself to
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paul@37 | 173 | be discharged from providing access to memory, potentially for a range of
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paul@37 | 174 | addresses, and for the CPU to communicate with external memory uninterrupted.
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paul@33 | 175 |
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paul@0 | 176 | Hardware Scrolling
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paul@0 | 177 | ------------------
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paul@0 | 178 |
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paul@0 | 179 | On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
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paul@0 | 180 | the least significant 5 bits being zero, thus limiting the scrolling
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paul@0 | 181 | resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
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paul@0 | 182 | using the same layout of these addresses.
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paul@0 | 183 |
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paul@0 | 184 | |--&FE02--------------| |--&FE03--------------|
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paul@0 | 185 | XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
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paul@0 | 186 |
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paul@0 | 187 | XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
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paul@0 | 188 |
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paul@4 | 189 | Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
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paul@4 | 190 | memory to pixel locations is character oriented. A change in 8 bytes would
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paul@4 | 191 | permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
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paul@4 | 192 | MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
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paul@4 | 193 | observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
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paul@4 | 194 | Guide).
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paul@4 | 195 |
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paul@4 | 196 | One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
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paul@4 | 197 | of changing the screen address by 2 bytes is the change in the number of lines
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paul@4 | 198 | from the initial and final character rows that need reading by the ULA, which
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paul@9 | 199 | would need to maintain this state information (although this is a relatively
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paul@9 | 200 | trivial change). Another pitfall is the complication that might be introduced
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paul@9 | 201 | to software writing bitmaps of character height to the screen.
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paul@4 | 202 |
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paul@4 | 203 | Region Blanking
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paul@4 | 204 | ---------------
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paul@4 | 205 |
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paul@4 | 206 | The problem of permitting character-oriented blitting in programs whilst
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paul@4 | 207 | scrolling the screen by sub-character amounts could be mitigated by permitting
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paul@4 | 208 | a region of the display to be blank, such as the final lines of the display.
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paul@4 | 209 | Consider the following vertical scrolling by 2 bytes that would cause an
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paul@4 | 210 | initial character row of 6 lines and a final character row of 2 lines:
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paul@4 | 211 |
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paul@4 | 212 | 6 lines - initial, partial character row
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paul@4 | 213 | 248 lines - 31 complete rows
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paul@4 | 214 | 2 lines - final, partial character row
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paul@4 | 215 |
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paul@4 | 216 | If a routine were in use that wrote 8 line bitmaps to the partial character
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paul@4 | 217 | row now split in two, it would be advisable to hide one of the regions in
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paul@4 | 218 | order to prevent content appearing in the wrong place on screen (such as
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paul@4 | 219 | content meant to appear at the top "leaking" onto the bottom). Blanking 6
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paul@4 | 220 | lines would be sufficient, as can be seen from the following cases.
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paul@4 | 221 |
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paul@4 | 222 | Scrolling up by 2 lines:
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paul@4 | 223 |
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paul@4 | 224 | 6 lines - initial, partial character row
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paul@4 | 225 | 240 lines - 30 complete rows
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paul@4 | 226 | 4 lines - part of 1 complete row
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paul@4 | 227 | -----------------------------------------------------------------
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paul@4 | 228 | 4 lines - part of 1 complete row (hidden to maintain 250 lines)
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paul@4 | 229 | 2 lines - final, partial character row (hidden)
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paul@4 | 230 |
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paul@4 | 231 | Scrolling down by 2 lines:
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paul@4 | 232 |
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paul@4 | 233 | 2 lines - initial, partial character row
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paul@4 | 234 | 248 lines - 31 complete rows
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paul@4 | 235 | ----------------------------------------------------------
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paul@4 | 236 | 6 lines - final, partial character row (hidden)
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paul@4 | 237 |
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paul@24 | 238 | Thus, in this case, region blanking would impose a 250 line display with the
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paul@24 | 239 | bottom 6 lines blank.
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paul@24 | 240 |
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paul@24 | 241 | Screen Height Adjustment
|
paul@24 | 242 | ------------------------
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paul@24 | 243 |
|
paul@24 | 244 | The height of the screen could be configurable in order to reduce screen
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paul@24 | 245 | memory consumption. This is not quite done in MODE 3 and 6 since the start of
|
paul@24 | 246 | the screen appears to be rounded down to the nearest page, but by reducing the
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paul@24 | 247 | height by amounts more than a page, savings would be possible. For example:
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paul@24 | 248 |
|
paul@24 | 249 | Screen width Depth Height Bytes per line Saving in bytes Start address
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paul@24 | 250 | ------------ ----- ------ -------------- --------------- -------------
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paul@24 | 251 | 640 1 252 80 320 &3140 -> &3100
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paul@24 | 252 | 640 1 248 80 640 &3280 -> &3200
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paul@24 | 253 | 320 1 240 40 640 &5A80 -> &5A00
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paul@24 | 254 | 320 2 240 80 1280 &3500
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paul@0 | 255 |
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paul@0 | 256 | Palette Definition
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paul@0 | 257 | ------------------
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paul@0 | 258 |
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paul@0 | 259 | Since all memory accesses go via the ULA, an enhanced ULA could employ more
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paul@0 | 260 | specific addresses than &FE*X to perform enhanced functions. For example, the
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paul@0 | 261 | palette control is done using &FE*8-F and merely involves selecting predefined
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paul@0 | 262 | colours, whereas an enhanced ULA could support the redefinition of all 16
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paul@0 | 263 | colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
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paul@0 | 264 | (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
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paul@0 | 265 | specifications similar to those used on the Archimedes.
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paul@0 | 266 |
|
paul@4 | 267 | The principal limitation here is actually the hardware: the Electron has only
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paul@4 | 268 | a single output line for each of the red, green and blue channels, and if
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paul@4 | 269 | those outputs are strictly digital and can only be set to a "high" and "low"
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paul@4 | 270 | value, then only the existing eight colours are possible. If a modern ULA were
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paul@4 | 271 | able to output analogue values, it would still need to be assessed whether the
|
paul@4 | 272 | circuitry could successfully handle and propagate such values.
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paul@4 | 273 |
|
paul@4 | 274 | Palette Definition Lists
|
paul@4 | 275 | ------------------------
|
paul@4 | 276 |
|
paul@4 | 277 | It can be useful to redefine the palette in order to change the colours
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paul@4 | 278 | available for a particular region of the screen, particularly in modes where
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paul@4 | 279 | the choice of colours is constrained, and if an increased colour depth were
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paul@4 | 280 | available, palette redefinition would be useful to give the illusion of more
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paul@4 | 281 | than 16 colours in MODE 2. Traditionally, palette redefinition has been done
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paul@4 | 282 | by using interrupt-driven timers, but a more efficient approach would involve
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paul@4 | 283 | presenting lists of palette definitions to the ULA so that it can change the
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paul@4 | 284 | palette at a particular display line.
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paul@4 | 285 |
|
paul@4 | 286 | One might define a palette redefinition list in a region of memory and then
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paul@4 | 287 | communicate its contents to the ULA by writing the address and length of the
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paul@4 | 288 | list, along with the display line at which the palette is to be changed, to
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paul@4 | 289 | ULA registers such that the ULA buffers the list and performs the redefinition
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paul@4 | 290 | at the appropriate time. Throughput/bandwidth considerations might impose
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paul@4 | 291 | restrictions on the practical length of such a list, however.
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paul@4 | 292 |
|
paul@4 | 293 | Palette-Free Modes
|
paul@4 | 294 | ------------------
|
paul@4 | 295 |
|
paul@4 | 296 | Palette-free modes might be defined where bit values directly correspond to
|
paul@4 | 297 | the red, green and blue channels, although this would mostly make sense only
|
paul@4 | 298 | for modes with depths greater than the standard 4 bits per pixel, and such
|
paul@4 | 299 | modes would require more memory than MODE 2 if they were to have an acceptable
|
paul@4 | 300 | resolution.
|
paul@4 | 301 |
|
paul@4 | 302 | Display Suspend
|
paul@4 | 303 | ---------------
|
paul@4 | 304 |
|
paul@4 | 305 | Especially when writing to the screen memory, it could be beneficial to be
|
paul@4 | 306 | able to suspend the ULA's access to the memory, instead producing blank values
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paul@4 | 307 | for all screen pixels until a program is ready to reveal the screen. This is
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paul@4 | 308 | different from palette blanking since with a blank palette, the ULA is still
|
paul@4 | 309 | reading screen memory and translating its contents into pixel values that end
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paul@4 | 310 | up being blank.
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paul@4 | 311 |
|
paul@4 | 312 | This function is reminiscent of a capability of the ZX81, albeit necessary on
|
paul@4 | 313 | that hardware to reduce the load on the system CPU which was responsible for
|
paul@4 | 314 | producing the video output.
|
paul@4 | 315 |
|
paul@35 | 316 | Hardware Sprites
|
paul@35 | 317 | ----------------
|
paul@0 | 318 |
|
paul@0 | 319 | An enhanced ULA might provide hardware sprites, but this would be done in an
|
paul@0 | 320 | way that is incompatible with the standard ULA, since no &FE*X locations are
|
paul@34 | 321 | available for allocation. To keep the facility simple, hardware sprites would
|
paul@34 | 322 | have a standard byte width and height.
|
paul@34 | 323 |
|
paul@34 | 324 | The specification of sprites could involve the reservation of 16 locations
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paul@34 | 325 | (for example, &FE20-F) specifying a fixed number of eight sprites, with each
|
paul@34 | 326 | location pair referring to the sprite data. By limiting the ULA to dealing
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paul@34 | 327 | with a fixed number of sprites, the work required inside the ULA would be
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paul@35 | 328 | reduced since it would avoid having to deal with arbitrary numbers of sprites.
|
paul@0 | 329 |
|
paul@35 | 330 | The principal limitation on providing hardware sprites is that of having to
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paul@35 | 331 | obtain sprite data, given that the ULA is usually required to retrieve screen
|
paul@35 | 332 | data, and given the lack of memory bandwidth available to retrieve sprite data
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paul@35 | 333 | (particularly from multiple sprites supposedly at the same position) and
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paul@35 | 334 | screen data simultaneously. Although the ULA could potentially read sprite
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paul@35 | 335 | data and screen data in alternate memory accesses in screen modes where the
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paul@35 | 336 | bandwidth is not already fully utilised, this would result in a degradation of
|
paul@35 | 337 | performance.
|
paul@34 | 338 |
|
paul@24 | 339 | Additional Screen Mode Configurations
|
paul@24 | 340 | -------------------------------------
|
paul@24 | 341 |
|
paul@24 | 342 | Alternative screen mode configurations could be supported. The ULA has to
|
paul@24 | 343 | produce 640 pixel values across the screen, with pixel doubling or quadrupling
|
paul@24 | 344 | employed to fill the screen width:
|
paul@24 | 345 |
|
paul@24 | 346 | Screen width Columns Scaling Depth Bytes
|
paul@24 | 347 | ------------ ------- ------- ----- -----
|
paul@24 | 348 | 640 80 x1 1 80
|
paul@24 | 349 | 320 40 x2 1, 2 40, 80
|
paul@24 | 350 | 160 20 x4 2, 4 40, 80
|
paul@24 | 351 |
|
paul@24 | 352 | It must also use at most 80 byte-sized memory accesses to provide the
|
paul@24 | 353 | information for the display. Given that characters must occupy an 8x8 pixel
|
paul@24 | 354 | array, if a configuration featuring anything other than 20, 40 or 80 character
|
paul@24 | 355 | columns is to be supported, compromises must be made such as the introduction
|
paul@24 | 356 | of blank pixels either between characters (such as occurs between rows in MODE
|
paul@24 | 357 | 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
|
paul@24 | 358 | in MODE 3 and 6). Consider the following configuration:
|
paul@24 | 359 |
|
paul@24 | 360 | Screen width Columns Scaling Depth Bytes Blank
|
paul@24 | 361 | ------------ ------- ------- ----- ------ -----
|
paul@24 | 362 | 208 26 x3 1, 2 26, 52 16
|
paul@24 | 363 |
|
paul@24 | 364 | Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
|
paul@24 | 365 | colours could be provided, with 16 blank pixel values (out of a total of 640)
|
paul@24 | 366 | generated either at the start or end (or split between the start and end) of
|
paul@24 | 367 | each scanline.
|
paul@24 | 368 |
|
paul@24 | 369 | Character Attributes
|
paul@24 | 370 | --------------------
|
paul@24 | 371 |
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paul@24 | 372 | The BBC Micro MODE 7 employs something resembling character attributes to
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paul@24 | 373 | support teletext displays, but depends on circuitry providing a character
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paul@24 | 374 | generator. The ZX Spectrum, on the other hand, provides character attributes
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paul@24 | 375 | as a means of colouring bitmapped graphics. Although such a feature is very
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paul@24 | 376 | limiting as the sole means of providing multicolour graphics, in situations
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paul@24 | 377 | where the choice is between low resolution multicolour graphics or high
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paul@24 | 378 | resolution monochrome graphics, character attributes provide a potentially
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paul@24 | 379 | useful compromise.
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paul@24 | 380 |
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paul@24 | 381 | For each byte read, the ULA must deliver 8 pixel values (out of a total of
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paul@24 | 382 | 640) to the video output, doing so by either emptying its pixel buffer on a
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paul@24 | 383 | pixel per cycle basis, or by multiplying pixels and thus holding them for more
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paul@24 | 384 | than one cycle. For example for a screen mode having 640 pixels in width:
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paul@24 | 385 |
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paul@24 | 386 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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paul@24 | 387 | Reads: B B
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paul@24 | 388 | Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
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paul@24 | 389 |
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paul@24 | 390 | And for a screen mode having 320 pixels in width:
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paul@24 | 391 |
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paul@24 | 392 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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paul@24 | 393 | Reads: B
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paul@24 | 394 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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paul@24 | 395 |
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paul@24 | 396 | However, in modes where less than 80 bytes are required to generate the pixel
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paul@24 | 397 | values, an enhanced ULA might be able to read additional bytes between those
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paul@24 | 398 | providing the bitmapped graphics data:
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paul@24 | 399 |
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paul@24 | 400 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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paul@24 | 401 | Reads: B A
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paul@24 | 402 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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paul@24 | 403 |
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paul@24 | 404 | These additional bytes could provide colour information for the bitmapped data
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paul@24 | 405 | in the following character column (of 8 pixels). Since it would be desirable
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paul@24 | 406 | to apply attribute data to the first column, the initial 8 cycles might be
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paul@24 | 407 | configured to not produce pixel values.
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paul@24 | 408 |
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paul@35 | 409 | For an entire character, attribute data need only be read for the first row of
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paul@35 | 410 | pixels for a character. The subsequent rows would have attribute information
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paul@35 | 411 | applied to them, although this would require the attribute data to be stored
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paul@35 | 412 | in some kind of buffer. Thus, the following access pattern would be observed:
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paul@35 | 413 |
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paul@35 | 414 | Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
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paul@35 | 415 |
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paul@24 | 416 | A whole byte used for colour information for a whole character would result in
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paul@35 | 417 | a choice of 256 colours, and this might be somewhat excessive. By only reading
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paul@35 | 418 | attribute bytes at every other opportunity, a choice of 16 colours could be
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paul@35 | 419 | applied individually to two characters.
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paul@24 | 420 |
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paul@24 | 421 | Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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paul@24 | 422 | Reads: B A B -
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paul@24 | 423 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
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paul@24 | 424 |
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paul@35 | 425 | Further reductions in attribute data access, offering 4 colours for every
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paul@35 | 426 | character in a four character block, for example, might also be worth
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paul@34 | 427 | considering.
|
paul@34 | 428 |
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paul@24 | 429 | Consider the following configurations for screen modes with a colour depth of
|
paul@24 | 430 | 1 bit per pixel for bitmap information:
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paul@24 | 431 |
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paul@35 | 432 | Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
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paul@35 | 433 | ------------ ------- ------- --------- --------- ------- ------------
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paul@35 | 434 | 320 40 x2 40 40 256 &5300
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paul@35 | 435 | 320 40 x2 40 20 16 &5580 -> &5500
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paul@35 | 436 | 320 40 x2 40 10 4 &56C0 -> &5600
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paul@35 | 437 | 208 26 x3 26 26 256 &62C0 -> &6200
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paul@35 | 438 | 208 26 x3 26 13 16 &6460 -> &6400
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paul@34 | 439 |
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paul@34 | 440 | MODE 7 Emulation using Character Attributes
|
paul@34 | 441 | -------------------------------------------
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paul@24 | 442 |
|
paul@24 | 443 | If the scheme of applying attributes to character regions were employed to
|
paul@24 | 444 | emulate MODE 7, in conjunction with the MODE 6 display technique, the
|
paul@24 | 445 | following configuration would be required:
|
paul@24 | 446 |
|
paul@24 | 447 | Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
|
paul@24 | 448 | ------------ ------- ---- --------- --------- ------- ------------
|
paul@35 | 449 | 320 40 25 40 20 16 &5ECC -> &5E00
|
paul@35 | 450 | 320 40 25 40 10 4 &5FC6 -> &5F00
|
paul@24 | 451 |
|
paul@35 | 452 | Although this requires much more memory than MODE 7 (8500 bytes versus MODE
|
paul@35 | 453 | 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
|
paul@35 | 454 | at least make a limited 40-column multicolour mode available as a substitute
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paul@35 | 455 | for MODE 7.
|
paul@24 | 456 |
|
paul@24 | 457 | Enhanced Graphics and Mode Layouts
|
paul@24 | 458 | ----------------------------------
|
paul@0 | 459 |
|
paul@0 | 460 | Screen modes with different screen memory mappings, higher resolutions and
|
paul@0 | 461 | larger colour depths might be possible, but this would in most cases involve
|
paul@0 | 462 | the allocation of more screen memory, and the ULA would probably then be
|
paul@0 | 463 | obliged to page in such memory for the CPU to be able to sensibly access it
|
paul@0 | 464 | all. Merely changing the memory mappings in order to have Archimedes-style
|
paul@0 | 465 | row-oriented screen addresses (instead of character-oriented addresses) could
|
paul@0 | 466 | be done for the existing modes, but this might not be sufficiently beneficial,
|
paul@0 | 467 | especially since accessing regions of the screen would involve incrementing
|
paul@0 | 468 | pointers by amounts that are inconvenient on an 8-bit CPU.
|
paul@0 | 469 |
|
paul@0 | 470 | Enhanced Sound
|
paul@0 | 471 | --------------
|
paul@0 | 472 |
|
paul@0 | 473 | The standard ULA reserves &FE*6 for sound generation and cassette
|
paul@0 | 474 | input/output, thus making it impossible to support multiple channels within
|
paul@0 | 475 | the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
|
paul@0 | 476 | and an enhanced ULA could adopt this interface.
|
paul@0 | 477 |
|
paul@9 | 478 | The BBC Micro uses the SN76489 chip to produce sound, and the entire
|
paul@9 | 479 | functionality of this chip could be emulated for enhanced sound, with a subset
|
paul@9 | 480 | of the functionality exposed via the &FE*6 interface.
|
paul@9 | 481 |
|
paul@9 | 482 | See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
|
paul@9 | 483 |
|
paul@0 | 484 | Waveform Upload
|
paul@0 | 485 | ---------------
|
paul@0 | 486 |
|
paul@0 | 487 | As with a hardware sprite function, waveforms could be uploaded or referenced
|
paul@0 | 488 | using locations as registers referencing memory regions.
|
paul@0 | 489 |
|
paul@0 | 490 | BBC ULA Compatibility
|
paul@0 | 491 | ---------------------
|
paul@0 | 492 |
|
paul@0 | 493 | Although some new ULA functions could be defined in a way that is also
|
paul@0 | 494 | compatible with the BBC Micro, the BBC ULA is itself incompatible with the
|
paul@0 | 495 | Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
|
paul@0 | 496 | map, but controls various functions specific to the 6845 video controller;
|
paul@0 | 497 | &FE08-F is reserved for the serial controller. It therefore becomes possible
|
paul@0 | 498 | to disregard compatibility where compatibility is already disregarded for a
|
paul@0 | 499 | particular area of functionality.
|
paul@0 | 500 |
|
paul@0 | 501 | &FE20-F maps to video ULA functionality on the BBC Micro which provides
|
paul@0 | 502 | control over the palette (using address &FE21, compared to &FE07-F on the
|
paul@0 | 503 | Electron) and other system-specific functions. Since the location usage is
|
paul@0 | 504 | generally incompatible, this region could be reused for other purposes.
|
paul@31 | 505 |
|
paul@31 | 506 | ULA Pin Functions
|
paul@31 | 507 | -----------------
|
paul@31 | 508 |
|
paul@31 | 509 | The functions of the ULA pins are described in the Electron Service Manual. Of
|
paul@31 | 510 | interest to video processing are the following:
|
paul@31 | 511 |
|
paul@31 | 512 | CSYNC (low during horizontal or vertical synchronisation periods, high
|
paul@31 | 513 | otherwise)
|
paul@31 | 514 |
|
paul@31 | 515 | HS (low during horizontal synchronisation periods, high otherwise)
|
paul@31 | 516 |
|
paul@31 | 517 | RED, GREEN, BLUE (pixel colour outputs)
|
paul@31 | 518 |
|
paul@31 | 519 | CLOCK IN (a 16MHz clock input, 4V peak to peak)
|
paul@31 | 520 |
|
paul@31 | 521 | PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
|
paul@31 | 522 |
|
paul@31 | 523 | More general memory access pins:
|
paul@31 | 524 |
|
paul@31 | 525 | RAM0...RAM3 (data lines to/from the RAM)
|
paul@31 | 526 |
|
paul@31 | 527 | RA0...RA7 (address lines for sending both row and column addresses to the RAM)
|
paul@31 | 528 |
|
paul@38 | 529 | RAS (row address strobe setting the row address on a negative edge - see the
|
paul@38 | 530 | timing notes)
|
paul@31 | 531 |
|
paul@38 | 532 | CAS (column address strobe setting the column address on a negative edge -
|
paul@38 | 533 | see the timing notes)
|
paul@31 | 534 |
|
paul@31 | 535 | WE (sets write enable with logic 0, read with logic 1)
|
paul@31 | 536 |
|
paul@31 | 537 | ROM (select data access from ROM)
|
paul@31 | 538 |
|
paul@31 | 539 | CPU-oriented memory access pins:
|
paul@31 | 540 |
|
paul@31 | 541 | A0...A15 (CPU address lines)
|
paul@31 | 542 |
|
paul@31 | 543 | PD0...PD7 (CPU data lines)
|
paul@31 | 544 |
|
paul@31 | 545 | R/W (indicates CPU write with logic 0, CPU read with logic 1)
|
paul@31 | 546 |
|
paul@31 | 547 | Interrupt-related pins:
|
paul@31 | 548 |
|
paul@31 | 549 | NMI (CPU request for uninterrupted 1MHz access to memory)
|
paul@31 | 550 |
|
paul@31 | 551 | IRQ (signal event to CPU)
|
paul@31 | 552 |
|
paul@31 | 553 | POR (power-on reset, resetting the ULA on a positive edge and asserting the
|
paul@31 | 554 | CPU's RST pin)
|
paul@31 | 555 |
|
paul@31 | 556 | RST (master reset for the CPU signalled on power-up and by the Break key)
|
paul@31 | 557 |
|
paul@31 | 558 | Keyboard-related pins:
|
paul@31 | 559 |
|
paul@31 | 560 | KBD0...KBD3 (keyboard inputs)
|
paul@31 | 561 |
|
paul@31 | 562 | CAPS LOCK (control status LED)
|
paul@31 | 563 |
|
paul@31 | 564 | Sound-related pins:
|
paul@31 | 565 |
|
paul@31 | 566 | SOUND O/P (sound output using internal oscillator)
|
paul@31 | 567 |
|
paul@31 | 568 | Cassette-related pins:
|
paul@31 | 569 |
|
paul@31 | 570 | CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
|
paul@31 | 571 |
|
paul@31 | 572 | CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
|
paul@31 | 573 |
|
paul@31 | 574 | CAS RC (detect high tone)
|
paul@31 | 575 |
|
paul@31 | 576 | CAS MO (motor relay output)
|
paul@31 | 577 |
|
paul@31 | 578 | ÷13 IN (~1200 baud clock input)
|