paul@46 | 1 | Principal Design and Feature Constraints
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paul@46 | 2 | ----------------------------------------
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paul@46 | 3 |
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paul@46 | 4 | The features of the ULA are limited by the amount of time and resources that
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paul@46 | 5 | can be allocated to each activity necessary to support such features given the
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paul@46 | 6 | fundamental obligations of the unit. Maintaining a screen display based on the
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paul@46 | 7 | contents of RAM itself requires the ULA to have exclusive access to such
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paul@46 | 8 | hardware resources for a significant period of time. Whilst other elements of
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paul@46 | 9 | the ULA can in principle run in parallel with this activity, they cannot also
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paul@46 | 10 | access the RAM. Consequently, other features that might use the RAM must
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paul@46 | 11 | accept a reduced allocation of that resource in comparison to a hypothetical
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paul@46 | 12 | architecture where concurrent RAM access is possible.
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paul@46 | 13 |
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paul@46 | 14 | Thus, the principal constraint for many features is bandwidth. The duration of
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paul@46 | 15 | access to hardware resources is one aspect of this; the rate at which such
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paul@46 | 16 | resources can be accessed is another. For example, the RAM is not fast enough
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paul@46 | 17 | to support access more frequently than one byte per 2MHz cycle, and for screen
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paul@46 | 18 | modes involving 80 bytes of screen data per scanline, there are no free cycles
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paul@46 | 19 | for anything other than the production of pixel output during the active
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paul@46 | 20 | scanline periods.
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paul@46 | 21 |
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paul@22 | 22 | Timing
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paul@22 | 23 | ------
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paul@22 | 24 |
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paul@40 | 25 | According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
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paul@40 | 26 | of which are used to generate pixel data. At 50Hz, this means that 128 cycles
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paul@40 | 27 | are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
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paul@40 | 28 | 312 ~= 128 cycles). This is consistent with the observation that each scanline
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paul@37 | 29 | requires at most 80 bytes of data, and that the ULA is apparently busy for 40
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paul@37 | 30 | out of 64 microseconds in each scanline.
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paul@22 | 31 |
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paul@33 | 32 | Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
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paul@33 | 33 | each providing two bits of each byte) using two cycles within the 500ns period
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paul@36 | 34 | of the 2MHz clock to complete each access operation. Since the CPU and ULA
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paul@36 | 35 | have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
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paul@36 | 36 | effectively run at 1MHz (since every other 500ns period involves the ULA
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paul@36 | 37 | accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
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paul@36 | 38 | frequency is divided by the ULA (IC1) depending on the screen mode in use.
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paul@33 | 39 |
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paul@37 | 40 | Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
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paul@37 | 41 | patterns corresponding to 16MHz cycles are required:
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paul@37 | 42 |
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paul@39 | 43 | Time (ns): 0-------------- 500------------ ...
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paul@37 | 44 | 2 MHz cycle: 0 1 ...
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paul@37 | 45 | 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
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paul@39 | 46 | ~RAS: 0 1 0 1 ...
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paul@39 | 47 | ~CAS: 0 1 0 1 0 1 0 1 ...
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paul@39 | 48 | A B B A B B ...
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paul@39 | 49 | F S F S ...
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paul@39 | 50 | a b b a b b ...
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paul@37 | 51 |
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paul@37 | 52 | Here, "A" indicates the row and column addresses being latched into the RAM
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paul@38 | 53 | (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
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paul@37 | 54 | second column address being latched into the RAM. Presumably, the first and
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paul@39 | 55 | second half-bytes can be read at "F" and "S" respectively, and the row and
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paul@39 | 56 | column addresses must be made available at "a" and "b" respectively at the
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paul@39 | 57 | latest.
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paul@37 | 58 |
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paul@38 | 59 | Note that the Service Manual refers to the negative edge of RAS and CAS, but
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paul@38 | 60 | the datasheet for the similar TM4164EC4 product shows latching on the negative
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paul@38 | 61 | edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
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paul@38 | 62 | communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
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paul@38 | 63 | "page mode" provides the appropriate behaviour for that particular product.
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paul@38 | 64 |
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paul@40 | 65 | Video Timing
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paul@40 | 66 | ------------
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paul@40 | 67 |
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paul@40 | 68 | According to 8.7 in the Service Manual, and the PAL Wikipedia page,
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paul@40 | 69 | approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
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paul@40 | 70 | (including the "colour burst"), and 1.65µs for the "front porch", totalling
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paul@40 | 71 | 12.05µs and thus leaving 51.95µs for the active video signal for each
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paul@40 | 72 | scanline. As the Service Manual suggests in the oscilloscope traces, the
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paul@40 | 73 | display information is transmitted more or less centred within the active
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paul@40 | 74 | video period since the ULA will only be providing pixel data for 40µs in each
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paul@40 | 75 | scanline.
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paul@39 | 76 |
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paul@39 | 77 | Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
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paul@39 | 78 | each scanline can be divided into 1024 cycles, although only 640 at most are
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paul@40 | 79 | actively used to provide pixel data. Pixel data production should only occur
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paul@40 | 80 | within a certain period on each scanline, approximately 262 cycles after the
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paul@40 | 81 | start of hsync:
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paul@40 | 82 |
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paul@40 | 83 | active video period = 51.95µs
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paul@40 | 84 | pixel data period = 40µs
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paul@40 | 85 | total silent period = 51.95µs - 40µs = 11.95µs
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paul@40 | 86 | silent periods (before and after) = 11.95µs / 2 = 5.975µs
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paul@40 | 87 | hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
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paul@40 | 88 | time before pixel data period = 10.4µs + 5.975µs = 16.375µs
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paul@40 | 89 | pixel data period start cycle = 16.375µs / 62.5ns = 262
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paul@40 | 90 |
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paul@40 | 91 | By choosing a number divisible by 8, the RAM access mechanism can be
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paul@40 | 92 | synchronised with the pixel production. Thus, 264 is a more appropriate start
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paul@40 | 93 | cycle.
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paul@40 | 94 |
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paul@40 | 95 | The "vertical blanking period", meaning the period before picture information
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paul@40 | 96 | in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
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paul@40 | 97 | 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
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paul@40 | 98 | for 2.5 lines. Thus, the first visible scanline on the first field of a frame
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paul@40 | 99 | occurs half way through the 23rd scanline period measured from the start of
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paul@40 | 100 | vsync:
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paul@40 | 101 |
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paul@40 | 102 | 10 20 23
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paul@40 | 103 | Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
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paul@40 | 104 | Line from 1: 0 22 3
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paul@40 | 105 | Line on screen: .:::::VVVVV::::: 12233445566
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paul@40 | 106 | |_________________________________________________|
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paul@40 | 107 | 25 line vertical blanking period
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paul@40 | 108 |
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paul@40 | 109 | In the second field of a frame, the first visible scanline coincides with the
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paul@40 | 110 | 24th scanline period measured from the start of line 313 in the frame:
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paul@40 | 111 |
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paul@40 | 112 | 310 336
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paul@40 | 113 | Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
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paul@40 | 114 | Line from 313: 0 23
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paul@40 | 115 | Line on screen: 88:::::VVVVV:::: 11223344
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paul@40 | 116 | 288 | |
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paul@40 | 117 | |_________________________________________________|
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paul@40 | 118 | 25 line vertical blanking period
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paul@40 | 119 |
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paul@40 | 120 | In order to consider only full lines, we might consider the start of each
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paul@40 | 121 | frame to occur 23 lines after the start of vsync.
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paul@40 | 122 |
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paul@40 | 123 | Again, it is likely that pixel data production should only occur on scanlines
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paul@40 | 124 | within a certain period on each frame. The "625/50" document indicates that
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paul@40 | 125 | only a certain region is "safe" to use, suggesting a vertically centred region
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paul@40 | 126 | with approximately 15 blank lines above and below the picture. Thus, the start
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paul@40 | 127 | of the picture could be chosen as 38 lines after the start of vsync.
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paul@40 | 128 |
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paul@56 | 129 | RAM Integrated Circuits
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paul@56 | 130 | -----------------------
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paul@56 | 131 |
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paul@56 | 132 | The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
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paul@56 | 133 | the Samsung-produced KM4164 series is apparently equivalent to the Texas
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paul@56 | 134 | Instruments 4164 chips presumably used in the Electron.
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paul@56 | 135 |
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paul@56 | 136 | The TM4164EC4 series combines 4 64K x 1b units into a single package and
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paul@56 | 137 | presumably could be used to replace the Electron's separate ICs, but it has 22
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paul@56 | 138 | pins providing 3 additional inputs and 3 additional outputs over the 16 pins
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paul@56 | 139 | of the existing modules, presumably allowing concurrent access to the packaged
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paul@56 | 140 | memory units.
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paul@56 | 141 |
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paul@56 | 142 | As far as currently available replacements are concerned, the NTE4164 is a
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paul@56 | 143 | potential candidate. According to the Vetco Electronics entry, it is
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paul@56 | 144 | supposedly a replacement for the TMS4164-15 amongst others. Meanwhile, the
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paul@56 | 145 | NTE21256 appears to be a 16-pin replacement for all four ICs that maintains
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paul@56 | 146 | the single data input and output pins.
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paul@56 | 147 |
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paul@40 | 148 | See: Acorn Electron Advanced User Guide
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paul@40 | 149 | See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
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paul@40 | 150 | See: http://en.wikipedia.org/wiki/PAL
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paul@40 | 151 | See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
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paul@40 | 152 | See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
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paul@40 | 153 | http://lipas.uwasa.fi/~f76998/video/modes/
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paul@40 | 154 | See: PAL TV timing and voltages
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paul@40 | 155 | http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
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paul@40 | 156 | See: Line Standards
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paul@40 | 157 | http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
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paul@40 | 158 | See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
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paul@40 | 159 | http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
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paul@56 | 160 | See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
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paul@56 | 161 | http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
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paul@56 | 162 | See: NTE4164 - IC-NMOS 64K DRAM 150NS
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paul@56 | 163 | http://www.vetco.net/catalog/product_info.php?products_id=3680
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paul@56 | 164 | See: NTE21256 - IC-256K DRAM 150NS
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paul@56 | 165 | http://www.vetco.net/catalog/product_info.php?products_id=2799
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paul@56 | 166 | See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
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paul@56 | 167 | http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
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paul@40 | 168 | See: Acorn Electron Service Manual
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paul@40 | 169 | http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
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paul@39 | 170 |
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paul@43 | 171 | Interrupts
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paul@43 | 172 | ----------
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paul@43 | 173 |
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paul@43 | 174 | The ULA generates IRQs (maskable interrupts) according to certain conditions
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paul@43 | 175 | and these conditions are controlled by location &FE00:
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paul@43 | 176 |
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paul@43 | 177 | * Vertical sync (bottom of displayed screen)
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paul@43 | 178 | * 50MHz real time clock
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paul@43 | 179 | * Transmit data empty
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paul@43 | 180 | * Receive data full
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paul@43 | 181 | * High tone detect
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paul@43 | 182 |
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paul@43 | 183 | The ULA is also used to clear interrupt conditions through location &FE05. Of
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paul@43 | 184 | particular significance is bit 7, which must be set if an NMI (non-maskable
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paul@43 | 185 | interrupt) has occurred and has thus suspended ULA access to memory, restoring
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paul@43 | 186 | the normal function of the ULA.
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paul@43 | 187 |
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paul@43 | 188 | ROM Paging
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paul@43 | 189 | ----------
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paul@43 | 190 |
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paul@43 | 191 | Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
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paul@43 | 192 | mappings exist:
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paul@43 | 193 |
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paul@43 | 194 | 8 keyboard
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paul@43 | 195 | 9 keyboard (duplicate)
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paul@43 | 196 | 10 BASIC ROM
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paul@43 | 197 | 11 BASIC ROM (duplicate)
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paul@43 | 198 |
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paul@43 | 199 | Paging in a ROM involves the following procedure:
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paul@43 | 200 |
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paul@43 | 201 | 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
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paul@43 | 202 | 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
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paul@43 | 203 | selected.
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paul@43 | 204 | 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
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paul@43 | 205 | whilst writing the desired ROM number n in bits 0 to 2.
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paul@43 | 206 |
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paul@37 | 207 | Shadow/Expanded Memory
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paul@37 | 208 | ----------------------
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paul@37 | 209 |
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paul@37 | 210 | The Electron exposes all sixteen address lines and all eight data lines
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paul@37 | 211 | through the expansion bus. Using such lines, it is possible to provide
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paul@37 | 212 | additional memory - typically sideways ROM and RAM - on expansion cards and
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paul@37 | 213 | through cartridges, although the official cartridge specification provides
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paul@37 | 214 | fewer address lines and only seeks to provide access to memory in 16K units.
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paul@37 | 215 |
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paul@37 | 216 | Various modifications and upgrades were developed to offer "turbo"
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paul@37 | 217 | capabilities to the Electron, permitting the CPU to access a separate 8K of
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paul@37 | 218 | RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
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paul@37 | 219 | the ULA through additional logic. However, an enhanced ULA might support
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paul@37 | 220 | independent CPU access to memory over the expansion bus by allowing itself to
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paul@37 | 221 | be discharged from providing access to memory, potentially for a range of
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paul@37 | 222 | addresses, and for the CPU to communicate with external memory uninterrupted.
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paul@33 | 223 |
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paul@0 | 224 | Hardware Scrolling
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paul@0 | 225 | ------------------
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paul@0 | 226 |
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paul@0 | 227 | On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
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paul@0 | 228 | the least significant 5 bits being zero, thus limiting the scrolling
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paul@0 | 229 | resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
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paul@0 | 230 | using the same layout of these addresses.
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paul@0 | 231 |
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paul@0 | 232 | |--&FE02--------------| |--&FE03--------------|
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paul@0 | 233 | XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
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paul@0 | 234 |
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paul@0 | 235 | XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
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paul@0 | 236 |
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paul@4 | 237 | Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
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paul@4 | 238 | memory to pixel locations is character oriented. A change in 8 bytes would
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paul@4 | 239 | permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
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paul@4 | 240 | MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
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paul@4 | 241 | observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
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paul@4 | 242 | Guide).
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paul@4 | 243 |
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paul@4 | 244 | One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
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paul@4 | 245 | of changing the screen address by 2 bytes is the change in the number of lines
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paul@4 | 246 | from the initial and final character rows that need reading by the ULA, which
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paul@9 | 247 | would need to maintain this state information (although this is a relatively
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paul@9 | 248 | trivial change). Another pitfall is the complication that might be introduced
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paul@9 | 249 | to software writing bitmaps of character height to the screen.
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paul@4 | 250 |
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paul@55 | 251 | Enhancement: Region Blanking
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paul@55 | 252 | ----------------------------
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paul@4 | 253 |
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paul@4 | 254 | The problem of permitting character-oriented blitting in programs whilst
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paul@4 | 255 | scrolling the screen by sub-character amounts could be mitigated by permitting
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paul@4 | 256 | a region of the display to be blank, such as the final lines of the display.
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paul@4 | 257 | Consider the following vertical scrolling by 2 bytes that would cause an
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paul@4 | 258 | initial character row of 6 lines and a final character row of 2 lines:
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paul@4 | 259 |
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paul@4 | 260 | 6 lines - initial, partial character row
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paul@4 | 261 | 248 lines - 31 complete rows
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paul@4 | 262 | 2 lines - final, partial character row
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paul@4 | 263 |
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paul@4 | 264 | If a routine were in use that wrote 8 line bitmaps to the partial character
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paul@4 | 265 | row now split in two, it would be advisable to hide one of the regions in
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paul@4 | 266 | order to prevent content appearing in the wrong place on screen (such as
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paul@4 | 267 | content meant to appear at the top "leaking" onto the bottom). Blanking 6
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paul@4 | 268 | lines would be sufficient, as can be seen from the following cases.
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paul@4 | 269 |
|
paul@4 | 270 | Scrolling up by 2 lines:
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paul@4 | 271 |
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paul@4 | 272 | 6 lines - initial, partial character row
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paul@4 | 273 | 240 lines - 30 complete rows
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paul@4 | 274 | 4 lines - part of 1 complete row
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paul@4 | 275 | -----------------------------------------------------------------
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paul@4 | 276 | 4 lines - part of 1 complete row (hidden to maintain 250 lines)
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paul@4 | 277 | 2 lines - final, partial character row (hidden)
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paul@4 | 278 |
|
paul@4 | 279 | Scrolling down by 2 lines:
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paul@4 | 280 |
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paul@4 | 281 | 2 lines - initial, partial character row
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paul@4 | 282 | 248 lines - 31 complete rows
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paul@4 | 283 | ----------------------------------------------------------
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paul@4 | 284 | 6 lines - final, partial character row (hidden)
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paul@4 | 285 |
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paul@24 | 286 | Thus, in this case, region blanking would impose a 250 line display with the
|
paul@24 | 287 | bottom 6 lines blank.
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paul@24 | 288 |
|
paul@55 | 289 | See the description of the display suspend enhancement for a more efficient
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paul@55 | 290 | way of blanking lines whilst allowing the CPU to perform useful work during
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paul@55 | 291 | the blanking period.
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paul@55 | 292 |
|
paul@55 | 293 | Enhancement: Screen Height Adjustment
|
paul@55 | 294 | -------------------------------------
|
paul@24 | 295 |
|
paul@24 | 296 | The height of the screen could be configurable in order to reduce screen
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paul@24 | 297 | memory consumption. This is not quite done in MODE 3 and 6 since the start of
|
paul@24 | 298 | the screen appears to be rounded down to the nearest page, but by reducing the
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paul@24 | 299 | height by amounts more than a page, savings would be possible. For example:
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paul@24 | 300 |
|
paul@24 | 301 | Screen width Depth Height Bytes per line Saving in bytes Start address
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paul@24 | 302 | ------------ ----- ------ -------------- --------------- -------------
|
paul@24 | 303 | 640 1 252 80 320 &3140 -> &3100
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paul@24 | 304 | 640 1 248 80 640 &3280 -> &3200
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paul@24 | 305 | 320 1 240 40 640 &5A80 -> &5A00
|
paul@24 | 306 | 320 2 240 80 1280 &3500
|
paul@0 | 307 |
|
paul@55 | 308 | Screen Mode Selection
|
paul@55 | 309 | ---------------------
|
paul@55 | 310 |
|
paul@55 | 311 | Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
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paul@55 | 312 | range of modes, the other bits of &FE*7 (related to sound, cassette
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paul@55 | 313 | input/output and the Caps Lock LED) would need to be reassigned and bit 0
|
paul@55 | 314 | potentially being made available for use.
|
paul@55 | 315 |
|
paul@0 | 316 | Palette Definition
|
paul@0 | 317 | ------------------
|
paul@0 | 318 |
|
paul@0 | 319 | Since all memory accesses go via the ULA, an enhanced ULA could employ more
|
paul@0 | 320 | specific addresses than &FE*X to perform enhanced functions. For example, the
|
paul@0 | 321 | palette control is done using &FE*8-F and merely involves selecting predefined
|
paul@0 | 322 | colours, whereas an enhanced ULA could support the redefinition of all 16
|
paul@0 | 323 | colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
|
paul@0 | 324 | (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
|
paul@0 | 325 | specifications similar to those used on the Archimedes.
|
paul@0 | 326 |
|
paul@4 | 327 | The principal limitation here is actually the hardware: the Electron has only
|
paul@4 | 328 | a single output line for each of the red, green and blue channels, and if
|
paul@4 | 329 | those outputs are strictly digital and can only be set to a "high" and "low"
|
paul@4 | 330 | value, then only the existing eight colours are possible. If a modern ULA were
|
paul@4 | 331 | able to output analogue values, it would still need to be assessed whether the
|
paul@46 | 332 | circuitry could successfully handle and propagate such values. Various sources
|
paul@46 | 333 | indicate that only "TTL levels" are supported by the RGB output circuit, and
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paul@46 | 334 | since there are 74LS08 AND logic gates involved in the RGB component outputs
|
paul@46 | 335 | from the ULA, it is likely that the ULA is expected to provide only "high" or
|
paul@46 | 336 | "low" values.
|
paul@4 | 337 |
|
paul@51 | 338 | Flashing Colours
|
paul@51 | 339 | ----------------
|
paul@51 | 340 |
|
paul@51 | 341 | According to the Advanced User Guide, "The cursor and flashing colours are
|
paul@51 | 342 | entirely generated in software: This means that all of the logical to physical
|
paul@51 | 343 | colour map must be changed to cause colours to flash." This appears to suggest
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paul@51 | 344 | that the palette registers must be updated upon the flash counter - read and
|
paul@51 | 345 | written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
|
paul@51 | 346 | colour pairs to be any combination of colours might be possible, instead of
|
paul@52 | 347 | having colour complements as pairs.
|
paul@52 | 348 |
|
paul@52 | 349 | It is conceivable that the interrupt code responsible does the simple thing
|
paul@54 | 350 | and merely inverts the current values for any logical colours (LC) for which
|
paul@54 | 351 | the associated physical colour (as supplied as the second parameter to the VDU
|
paul@54 | 352 | 19 call) has the top bit of its four bit value set. These top bits are not
|
paul@52 | 353 | recorded in the palette registers but are presumably recorded separately and
|
paul@52 | 354 | used to build bitmaps as follows:
|
paul@52 | 355 |
|
paul@54 | 356 | LC 2 colour 4 colour 16 colour 4-bit value for inversion
|
paul@54 | 357 | -- -------- -------- --------- -------------------------
|
paul@54 | 358 | 0 00010001 00010001 00010001 1, 1, 1
|
paul@54 | 359 | 1 01000100 00100010 00010001 4, 2, 1
|
paul@54 | 360 | 2 01000100 00100010 4, 2
|
paul@54 | 361 | 3 10001000 00100010 8, 2
|
paul@54 | 362 | 4 00010001 1
|
paul@54 | 363 | 5 00010001 1
|
paul@54 | 364 | 6 00100010 2
|
paul@54 | 365 | 7 00100010 2
|
paul@54 | 366 | 8 01000100 4
|
paul@54 | 367 | 9 01000100 4
|
paul@54 | 368 | 10 10001000 8
|
paul@54 | 369 | 11 10001000 8
|
paul@54 | 370 | 12 01000100 4
|
paul@54 | 371 | 13 01000100 4
|
paul@54 | 372 | 14 10001000 8
|
paul@54 | 373 | 15 10001000 8
|
paul@54 | 374 |
|
paul@54 | 375 | Inversion value calculation:
|
paul@54 | 376 |
|
paul@54 | 377 | 2 colour formula: 1 << (colour * 2)
|
paul@54 | 378 | 4 colour formula: 1 << colour
|
paul@54 | 379 | 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
|
paul@52 | 380 |
|
paul@53 | 381 | For example, where logical colour 0 has been mapped to a physical colour in
|
paul@53 | 382 | the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
|
paul@53 | 383 | the inversion operation. (The lower three bits of the physical colour would be
|
paul@53 | 384 | used to set the underlying colour information affected by the inversion
|
paul@53 | 385 | operation.)
|
paul@53 | 386 |
|
paul@52 | 387 | An operation in the interrupt code would then combine the bitmaps for all
|
paul@52 | 388 | logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
|
paul@52 | 389 | combined for groups of logical colours as follows:
|
paul@52 | 390 |
|
paul@54 | 391 | Logical colours
|
paul@54 | 392 | ---------------
|
paul@52 | 393 | 0, 2, 8, 10
|
paul@52 | 394 | 4, 6, 12, 14
|
paul@52 | 395 | 5, 7, 13, 15
|
paul@52 | 396 | 1, 3, 9, 11
|
paul@52 | 397 |
|
paul@52 | 398 | These combined bitmaps would be EORed with the existing palette register
|
paul@52 | 399 | values in order to perform the value inversion necessary to produce the
|
paul@52 | 400 | flashing effect.
|
paul@51 | 401 |
|
paul@54 | 402 | Thus, in the VDU 19 operation, the appropriate inversion value would be
|
paul@54 | 403 | calculated for the logical colour, and this value would then be combined with
|
paul@54 | 404 | other inversion values in a dedicated memory location corresponding to the
|
paul@54 | 405 | colour's group as indicated above. Meanwhile, the palette channel values would
|
paul@54 | 406 | be derived from the lower three bits of the specified physical colour and
|
paul@54 | 407 | combined with other palette data in dedicated memory locations corresponding
|
paul@54 | 408 | to the palette registers.
|
paul@54 | 409 |
|
paul@55 | 410 | Enhancement: Palette Definition Lists
|
paul@55 | 411 | -------------------------------------
|
paul@4 | 412 |
|
paul@4 | 413 | It can be useful to redefine the palette in order to change the colours
|
paul@4 | 414 | available for a particular region of the screen, particularly in modes where
|
paul@4 | 415 | the choice of colours is constrained, and if an increased colour depth were
|
paul@4 | 416 | available, palette redefinition would be useful to give the illusion of more
|
paul@4 | 417 | than 16 colours in MODE 2. Traditionally, palette redefinition has been done
|
paul@4 | 418 | by using interrupt-driven timers, but a more efficient approach would involve
|
paul@4 | 419 | presenting lists of palette definitions to the ULA so that it can change the
|
paul@4 | 420 | palette at a particular display line.
|
paul@4 | 421 |
|
paul@4 | 422 | One might define a palette redefinition list in a region of memory and then
|
paul@4 | 423 | communicate its contents to the ULA by writing the address and length of the
|
paul@4 | 424 | list, along with the display line at which the palette is to be changed, to
|
paul@4 | 425 | ULA registers such that the ULA buffers the list and performs the redefinition
|
paul@4 | 426 | at the appropriate time. Throughput/bandwidth considerations might impose
|
paul@4 | 427 | restrictions on the practical length of such a list, however.
|
paul@4 | 428 |
|
paul@55 | 429 | Enhancement: Palette-Free Modes
|
paul@55 | 430 | -------------------------------
|
paul@4 | 431 |
|
paul@4 | 432 | Palette-free modes might be defined where bit values directly correspond to
|
paul@4 | 433 | the red, green and blue channels, although this would mostly make sense only
|
paul@4 | 434 | for modes with depths greater than the standard 4 bits per pixel, and such
|
paul@4 | 435 | modes would require more memory than MODE 2 if they were to have an acceptable
|
paul@4 | 436 | resolution.
|
paul@4 | 437 |
|
paul@55 | 438 | Enhancement: Display Suspend
|
paul@55 | 439 | ----------------------------
|
paul@4 | 440 |
|
paul@4 | 441 | Especially when writing to the screen memory, it could be beneficial to be
|
paul@4 | 442 | able to suspend the ULA's access to the memory, instead producing blank values
|
paul@4 | 443 | for all screen pixels until a program is ready to reveal the screen. This is
|
paul@4 | 444 | different from palette blanking since with a blank palette, the ULA is still
|
paul@4 | 445 | reading screen memory and translating its contents into pixel values that end
|
paul@4 | 446 | up being blank.
|
paul@4 | 447 |
|
paul@4 | 448 | This function is reminiscent of a capability of the ZX81, albeit necessary on
|
paul@4 | 449 | that hardware to reduce the load on the system CPU which was responsible for
|
paul@4 | 450 | producing the video output.
|
paul@4 | 451 |
|
paul@55 | 452 | Enhancement: Hardware Sprites
|
paul@55 | 453 | -----------------------------
|
paul@0 | 454 |
|
paul@0 | 455 | An enhanced ULA might provide hardware sprites, but this would be done in an
|
paul@0 | 456 | way that is incompatible with the standard ULA, since no &FE*X locations are
|
paul@34 | 457 | available for allocation. To keep the facility simple, hardware sprites would
|
paul@34 | 458 | have a standard byte width and height.
|
paul@34 | 459 |
|
paul@34 | 460 | The specification of sprites could involve the reservation of 16 locations
|
paul@34 | 461 | (for example, &FE20-F) specifying a fixed number of eight sprites, with each
|
paul@34 | 462 | location pair referring to the sprite data. By limiting the ULA to dealing
|
paul@34 | 463 | with a fixed number of sprites, the work required inside the ULA would be
|
paul@35 | 464 | reduced since it would avoid having to deal with arbitrary numbers of sprites.
|
paul@0 | 465 |
|
paul@35 | 466 | The principal limitation on providing hardware sprites is that of having to
|
paul@35 | 467 | obtain sprite data, given that the ULA is usually required to retrieve screen
|
paul@35 | 468 | data, and given the lack of memory bandwidth available to retrieve sprite data
|
paul@35 | 469 | (particularly from multiple sprites supposedly at the same position) and
|
paul@35 | 470 | screen data simultaneously. Although the ULA could potentially read sprite
|
paul@35 | 471 | data and screen data in alternate memory accesses in screen modes where the
|
paul@35 | 472 | bandwidth is not already fully utilised, this would result in a degradation of
|
paul@35 | 473 | performance.
|
paul@34 | 474 |
|
paul@55 | 475 | Enhancement: Additional Screen Mode Configurations
|
paul@55 | 476 | --------------------------------------------------
|
paul@24 | 477 |
|
paul@24 | 478 | Alternative screen mode configurations could be supported. The ULA has to
|
paul@24 | 479 | produce 640 pixel values across the screen, with pixel doubling or quadrupling
|
paul@24 | 480 | employed to fill the screen width:
|
paul@24 | 481 |
|
paul@24 | 482 | Screen width Columns Scaling Depth Bytes
|
paul@24 | 483 | ------------ ------- ------- ----- -----
|
paul@24 | 484 | 640 80 x1 1 80
|
paul@24 | 485 | 320 40 x2 1, 2 40, 80
|
paul@24 | 486 | 160 20 x4 2, 4 40, 80
|
paul@24 | 487 |
|
paul@24 | 488 | It must also use at most 80 byte-sized memory accesses to provide the
|
paul@24 | 489 | information for the display. Given that characters must occupy an 8x8 pixel
|
paul@24 | 490 | array, if a configuration featuring anything other than 20, 40 or 80 character
|
paul@24 | 491 | columns is to be supported, compromises must be made such as the introduction
|
paul@24 | 492 | of blank pixels either between characters (such as occurs between rows in MODE
|
paul@24 | 493 | 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
|
paul@55 | 494 | in MODE 3 and 6). Consider the following configuration:
|
paul@24 | 495 |
|
paul@24 | 496 | Screen width Columns Scaling Depth Bytes Blank
|
paul@24 | 497 | ------------ ------- ------- ----- ------ -----
|
paul@24 | 498 | 208 26 x3 1, 2 26, 52 16
|
paul@24 | 499 |
|
paul@24 | 500 | Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
|
paul@24 | 501 | colours could be provided, with 16 blank pixel values (out of a total of 640)
|
paul@24 | 502 | generated either at the start or end (or split between the start and end) of
|
paul@24 | 503 | each scanline.
|
paul@24 | 504 |
|
paul@55 | 505 | Enhancement: Character Attributes
|
paul@55 | 506 | ---------------------------------
|
paul@24 | 507 |
|
paul@24 | 508 | The BBC Micro MODE 7 employs something resembling character attributes to
|
paul@24 | 509 | support teletext displays, but depends on circuitry providing a character
|
paul@24 | 510 | generator. The ZX Spectrum, on the other hand, provides character attributes
|
paul@24 | 511 | as a means of colouring bitmapped graphics. Although such a feature is very
|
paul@24 | 512 | limiting as the sole means of providing multicolour graphics, in situations
|
paul@24 | 513 | where the choice is between low resolution multicolour graphics or high
|
paul@24 | 514 | resolution monochrome graphics, character attributes provide a potentially
|
paul@24 | 515 | useful compromise.
|
paul@24 | 516 |
|
paul@24 | 517 | For each byte read, the ULA must deliver 8 pixel values (out of a total of
|
paul@24 | 518 | 640) to the video output, doing so by either emptying its pixel buffer on a
|
paul@24 | 519 | pixel per cycle basis, or by multiplying pixels and thus holding them for more
|
paul@24 | 520 | than one cycle. For example for a screen mode having 640 pixels in width:
|
paul@24 | 521 |
|
paul@24 | 522 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
paul@24 | 523 | Reads: B B
|
paul@24 | 524 | Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
|
paul@24 | 525 |
|
paul@24 | 526 | And for a screen mode having 320 pixels in width:
|
paul@24 | 527 |
|
paul@24 | 528 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
paul@24 | 529 | Reads: B
|
paul@24 | 530 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
|
paul@24 | 531 |
|
paul@24 | 532 | However, in modes where less than 80 bytes are required to generate the pixel
|
paul@24 | 533 | values, an enhanced ULA might be able to read additional bytes between those
|
paul@24 | 534 | providing the bitmapped graphics data:
|
paul@24 | 535 |
|
paul@24 | 536 | Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
|
paul@24 | 537 | Reads: B A
|
paul@24 | 538 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
|
paul@24 | 539 |
|
paul@24 | 540 | These additional bytes could provide colour information for the bitmapped data
|
paul@24 | 541 | in the following character column (of 8 pixels). Since it would be desirable
|
paul@24 | 542 | to apply attribute data to the first column, the initial 8 cycles might be
|
paul@24 | 543 | configured to not produce pixel values.
|
paul@24 | 544 |
|
paul@35 | 545 | For an entire character, attribute data need only be read for the first row of
|
paul@35 | 546 | pixels for a character. The subsequent rows would have attribute information
|
paul@35 | 547 | applied to them, although this would require the attribute data to be stored
|
paul@35 | 548 | in some kind of buffer. Thus, the following access pattern would be observed:
|
paul@35 | 549 |
|
paul@35 | 550 | Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
|
paul@35 | 551 |
|
paul@24 | 552 | A whole byte used for colour information for a whole character would result in
|
paul@35 | 553 | a choice of 256 colours, and this might be somewhat excessive. By only reading
|
paul@35 | 554 | attribute bytes at every other opportunity, a choice of 16 colours could be
|
paul@35 | 555 | applied individually to two characters.
|
paul@24 | 556 |
|
paul@24 | 557 | Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
|
paul@24 | 558 | Reads: B A B -
|
paul@24 | 559 | Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
|
paul@24 | 560 |
|
paul@35 | 561 | Further reductions in attribute data access, offering 4 colours for every
|
paul@35 | 562 | character in a four character block, for example, might also be worth
|
paul@34 | 563 | considering.
|
paul@34 | 564 |
|
paul@24 | 565 | Consider the following configurations for screen modes with a colour depth of
|
paul@24 | 566 | 1 bit per pixel for bitmap information:
|
paul@24 | 567 |
|
paul@35 | 568 | Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
|
paul@35 | 569 | ------------ ------- ------- --------- --------- ------- ------------
|
paul@35 | 570 | 320 40 x2 40 40 256 &5300
|
paul@35 | 571 | 320 40 x2 40 20 16 &5580 -> &5500
|
paul@35 | 572 | 320 40 x2 40 10 4 &56C0 -> &5600
|
paul@35 | 573 | 208 26 x3 26 26 256 &62C0 -> &6200
|
paul@35 | 574 | 208 26 x3 26 13 16 &6460 -> &6400
|
paul@34 | 575 |
|
paul@55 | 576 | Enhancement: MODE 7 Emulation using Character Attributes
|
paul@55 | 577 | --------------------------------------------------------
|
paul@24 | 578 |
|
paul@24 | 579 | If the scheme of applying attributes to character regions were employed to
|
paul@24 | 580 | emulate MODE 7, in conjunction with the MODE 6 display technique, the
|
paul@24 | 581 | following configuration would be required:
|
paul@24 | 582 |
|
paul@24 | 583 | Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
|
paul@24 | 584 | ------------ ------- ---- --------- --------- ------- ------------
|
paul@35 | 585 | 320 40 25 40 20 16 &5ECC -> &5E00
|
paul@35 | 586 | 320 40 25 40 10 4 &5FC6 -> &5F00
|
paul@24 | 587 |
|
paul@35 | 588 | Although this requires much more memory than MODE 7 (8500 bytes versus MODE
|
paul@35 | 589 | 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
|
paul@35 | 590 | at least make a limited 40-column multicolour mode available as a substitute
|
paul@35 | 591 | for MODE 7.
|
paul@24 | 592 |
|
paul@55 | 593 | Enhancement: High Resolution Graphics and Mode Layouts
|
paul@55 | 594 | ------------------------------------------------------
|
paul@0 | 595 |
|
paul@0 | 596 | Screen modes with different screen memory mappings, higher resolutions and
|
paul@0 | 597 | larger colour depths might be possible, but this would in most cases involve
|
paul@0 | 598 | the allocation of more screen memory, and the ULA would probably then be
|
paul@0 | 599 | obliged to page in such memory for the CPU to be able to sensibly access it
|
paul@0 | 600 | all. Merely changing the memory mappings in order to have Archimedes-style
|
paul@0 | 601 | row-oriented screen addresses (instead of character-oriented addresses) could
|
paul@0 | 602 | be done for the existing modes, but this might not be sufficiently beneficial,
|
paul@0 | 603 | especially since accessing regions of the screen would involve incrementing
|
paul@0 | 604 | pointers by amounts that are inconvenient on an 8-bit CPU.
|
paul@0 | 605 |
|
paul@55 | 606 | Enhancement: Genlock Support
|
paul@55 | 607 | ----------------------------
|
paul@46 | 608 |
|
paul@46 | 609 | The ULA generates a video signal in conjunction with circuitry producing the
|
paul@46 | 610 | output features necessary for the correct display of the screen image.
|
paul@46 | 611 | However, it appears that the ULA drives the video synchronisation mechanism
|
paul@46 | 612 | instead of reacting to an existing signal. Genlock support might be possible
|
paul@46 | 613 | if the ULA were made to be responsive to such external signals, resetting its
|
paul@46 | 614 | address generators upon receiving synchronisation events.
|
paul@46 | 615 |
|
paul@55 | 616 | Enhancement: Improved Sound
|
paul@55 | 617 | ---------------------------
|
paul@0 | 618 |
|
paul@55 | 619 | The standard ULA reserves &FE*6 for sound generation and cassette input/output
|
paul@55 | 620 | (with bits 1 and 2 of &FE*7 being used to select either sound generation or
|
paul@55 | 621 | cassette I/O), thus making it impossible to support multiple channels within
|
paul@0 | 622 | the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
|
paul@0 | 623 | and an enhanced ULA could adopt this interface.
|
paul@0 | 624 |
|
paul@9 | 625 | The BBC Micro uses the SN76489 chip to produce sound, and the entire
|
paul@9 | 626 | functionality of this chip could be emulated for enhanced sound, with a subset
|
paul@9 | 627 | of the functionality exposed via the &FE*6 interface.
|
paul@9 | 628 |
|
paul@9 | 629 | See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
|
paul@9 | 630 |
|
paul@55 | 631 | Enhancement: Waveform Upload
|
paul@55 | 632 | ----------------------------
|
paul@0 | 633 |
|
paul@0 | 634 | As with a hardware sprite function, waveforms could be uploaded or referenced
|
paul@0 | 635 | using locations as registers referencing memory regions.
|
paul@0 | 636 |
|
paul@55 | 637 | Enhancement: Sound Input/Output
|
paul@55 | 638 | -------------------------------
|
paul@46 | 639 |
|
paul@46 | 640 | Since the ULA already controls audio input/output for cassette-based data, it
|
paul@46 | 641 | would have been interesting to entertain the idea of sampling and output of
|
paul@46 | 642 | sounds through the cassette interface. However, a significant amount of
|
paul@46 | 643 | circuitry is employed to process the input signal for use by the ULA and to
|
paul@46 | 644 | process the output signal for recording.
|
paul@46 | 645 |
|
paul@46 | 646 | See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
|
paul@46 | 647 |
|
paul@55 | 648 | Enhancement: BBC ULA Compatibility
|
paul@55 | 649 | ----------------------------------
|
paul@0 | 650 |
|
paul@0 | 651 | Although some new ULA functions could be defined in a way that is also
|
paul@0 | 652 | compatible with the BBC Micro, the BBC ULA is itself incompatible with the
|
paul@0 | 653 | Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
|
paul@0 | 654 | map, but controls various functions specific to the 6845 video controller;
|
paul@0 | 655 | &FE08-F is reserved for the serial controller. It therefore becomes possible
|
paul@0 | 656 | to disregard compatibility where compatibility is already disregarded for a
|
paul@0 | 657 | particular area of functionality.
|
paul@0 | 658 |
|
paul@0 | 659 | &FE20-F maps to video ULA functionality on the BBC Micro which provides
|
paul@0 | 660 | control over the palette (using address &FE21, compared to &FE07-F on the
|
paul@0 | 661 | Electron) and other system-specific functions. Since the location usage is
|
paul@0 | 662 | generally incompatible, this region could be reused for other purposes.
|
paul@31 | 663 |
|
paul@55 | 664 | Enhancement: Increased RAM, ULA and CPU Performance
|
paul@55 | 665 | ---------------------------------------------------
|
paul@49 | 666 |
|
paul@49 | 667 | More modern implementations of the hardware might feature faster RAM coupled
|
paul@49 | 668 | with an increased ULA clock frequency in order to increase the bandwidth
|
paul@49 | 669 | available to the ULA and to the CPU in situations where the ULA is not needed
|
paul@49 | 670 | to perform work. A ULA employing a 32MHz clock would be able to complete the
|
paul@49 | 671 | retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
|
paul@49 | 672 | to access the RAM for the following 250ns even in display modes requiring the
|
paul@49 | 673 | retrieval of a byte for the display every 500ns. The CPU could, subject to
|
paul@49 | 674 | timing issues, run at 2MHz even in MODE 0, 1 and 2.
|
paul@49 | 675 |
|
paul@49 | 676 | A scheme such as that described above would have a similar effect to the
|
paul@49 | 677 | scheme employed in the BBC Micro, although the latter made use of RAM with a
|
paul@49 | 678 | wider bandwidth in order to complete memory transfers within 250ns and thus
|
paul@49 | 679 | permit the CPU to run continuously at 2MHz.
|
paul@49 | 680 |
|
paul@49 | 681 | Higher bandwidth could potentially be used to implement exotic features such
|
paul@49 | 682 | as RAM-resident hardware sprites or indeed any feature demanding RAM access
|
paul@49 | 683 | concurrent with the production of the display image.
|
paul@49 | 684 |
|
paul@31 | 685 | ULA Pin Functions
|
paul@31 | 686 | -----------------
|
paul@31 | 687 |
|
paul@31 | 688 | The functions of the ULA pins are described in the Electron Service Manual. Of
|
paul@31 | 689 | interest to video processing are the following:
|
paul@31 | 690 |
|
paul@31 | 691 | CSYNC (low during horizontal or vertical synchronisation periods, high
|
paul@31 | 692 | otherwise)
|
paul@31 | 693 |
|
paul@31 | 694 | HS (low during horizontal synchronisation periods, high otherwise)
|
paul@31 | 695 |
|
paul@31 | 696 | RED, GREEN, BLUE (pixel colour outputs)
|
paul@31 | 697 |
|
paul@31 | 698 | CLOCK IN (a 16MHz clock input, 4V peak to peak)
|
paul@31 | 699 |
|
paul@31 | 700 | PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
|
paul@31 | 701 |
|
paul@31 | 702 | More general memory access pins:
|
paul@31 | 703 |
|
paul@31 | 704 | RAM0...RAM3 (data lines to/from the RAM)
|
paul@31 | 705 |
|
paul@31 | 706 | RA0...RA7 (address lines for sending both row and column addresses to the RAM)
|
paul@31 | 707 |
|
paul@38 | 708 | RAS (row address strobe setting the row address on a negative edge - see the
|
paul@38 | 709 | timing notes)
|
paul@31 | 710 |
|
paul@38 | 711 | CAS (column address strobe setting the column address on a negative edge -
|
paul@38 | 712 | see the timing notes)
|
paul@31 | 713 |
|
paul@31 | 714 | WE (sets write enable with logic 0, read with logic 1)
|
paul@31 | 715 |
|
paul@31 | 716 | ROM (select data access from ROM)
|
paul@31 | 717 |
|
paul@31 | 718 | CPU-oriented memory access pins:
|
paul@31 | 719 |
|
paul@31 | 720 | A0...A15 (CPU address lines)
|
paul@31 | 721 |
|
paul@31 | 722 | PD0...PD7 (CPU data lines)
|
paul@31 | 723 |
|
paul@31 | 724 | R/W (indicates CPU write with logic 0, CPU read with logic 1)
|
paul@31 | 725 |
|
paul@31 | 726 | Interrupt-related pins:
|
paul@31 | 727 |
|
paul@31 | 728 | NMI (CPU request for uninterrupted 1MHz access to memory)
|
paul@31 | 729 |
|
paul@31 | 730 | IRQ (signal event to CPU)
|
paul@31 | 731 |
|
paul@31 | 732 | POR (power-on reset, resetting the ULA on a positive edge and asserting the
|
paul@31 | 733 | CPU's RST pin)
|
paul@31 | 734 |
|
paul@31 | 735 | RST (master reset for the CPU signalled on power-up and by the Break key)
|
paul@31 | 736 |
|
paul@31 | 737 | Keyboard-related pins:
|
paul@31 | 738 |
|
paul@31 | 739 | KBD0...KBD3 (keyboard inputs)
|
paul@31 | 740 |
|
paul@31 | 741 | CAPS LOCK (control status LED)
|
paul@31 | 742 |
|
paul@31 | 743 | Sound-related pins:
|
paul@31 | 744 |
|
paul@31 | 745 | SOUND O/P (sound output using internal oscillator)
|
paul@31 | 746 |
|
paul@31 | 747 | Cassette-related pins:
|
paul@31 | 748 |
|
paul@31 | 749 | CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
|
paul@31 | 750 |
|
paul@31 | 751 | CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
|
paul@31 | 752 |
|
paul@31 | 753 | CAS RC (detect high tone)
|
paul@31 | 754 |
|
paul@31 | 755 | CAS MO (motor relay output)
|
paul@31 | 756 |
|
paul@31 | 757 | ÷13 IN (~1200 baud clock input)
|
paul@46 | 758 |
|
paul@46 | 759 | References
|
paul@46 | 760 | ----------
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paul@46 | 761 |
|
paul@46 | 762 | See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
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