paul@1 | 1 | #!/usr/bin/env python |
paul@1 | 2 | |
paul@1 | 3 | """ |
paul@1 | 4 | Acorn Electron ULA simulation. |
paul@71 | 5 | |
paul@84 | 6 | Copyright (C) 2011, 2012, 2013, 2014, 2016 Paul Boddie <paul@boddie.org.uk> |
paul@71 | 7 | |
paul@71 | 8 | This program is free software; you can redistribute it and/or modify it under |
paul@71 | 9 | the terms of the GNU General Public License as published by the Free Software |
paul@71 | 10 | Foundation; either version 3 of the License, or (at your option) any later |
paul@71 | 11 | version. |
paul@71 | 12 | |
paul@71 | 13 | This program is distributed in the hope that it will be useful, but WITHOUT ANY |
paul@71 | 14 | WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
paul@71 | 15 | PARTICULAR PURPOSE. See the GNU General Public License for more details. |
paul@71 | 16 | |
paul@71 | 17 | You should have received a copy of the GNU General Public License along |
paul@71 | 18 | with this program. If not, see <http://www.gnu.org/licenses/>. |
paul@1 | 19 | """ |
paul@1 | 20 | |
paul@29 | 21 | from array import array |
paul@29 | 22 | from itertools import repeat |
paul@29 | 23 | |
paul@22 | 24 | LINES_PER_ROW = 8 # the number of pixel lines per character row |
paul@22 | 25 | MAX_HEIGHT = 256 # the height of the screen in pixels |
paul@40 | 26 | MAX_WIDTH = 640 # the width of the screen in pixels |
paul@40 | 27 | |
paul@40 | 28 | MAX_CSYNC = 2 # the scanline during which vsync ends |
paul@84 | 29 | MIN_PIXELLINE = 28 # the first scanline involving pixel generation |
paul@22 | 30 | MAX_SCANLINE = 312 # the number of scanlines in each frame |
paul@40 | 31 | |
paul@40 | 32 | MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT |
paul@40 | 33 | |
paul@84 | 34 | MAX_HSYNC = 64 # the number of cycles in each hsync period |
paul@42 | 35 | MIN_PIXELPOS = 256 # the first cycle involving pixel generation |
paul@40 | 36 | MAX_SCANPOS = 1024 # the number of cycles in each scanline |
paul@40 | 37 | |
paul@40 | 38 | MAX_PIXELPOS = MIN_PIXELPOS + MAX_WIDTH |
paul@40 | 39 | |
paul@83 | 40 | PIXEL_POSITIONS = 8 # the number of pixel positions per byte |
paul@83 | 41 | # (doubled or quadrupled in lower resolutions) |
paul@83 | 42 | |
paul@22 | 43 | SCREEN_LIMIT = 0x8000 # the first address after the screen memory |
paul@22 | 44 | MAX_MEMORY = 0x10000 # the number of addressable memory locations |
paul@40 | 45 | MAX_RAM = 0x10000 # the number of addressable RAM locations (64Kb in each IC) |
paul@3 | 46 | BLANK = (0, 0, 0) |
paul@1 | 47 | |
paul@29 | 48 | def update(ula): |
paul@1 | 49 | |
paul@1 | 50 | """ |
paul@31 | 51 | Update the 'ula' for one frame. Return the resulting screen. |
paul@31 | 52 | """ |
paul@31 | 53 | |
paul@31 | 54 | video = ula.video |
paul@31 | 55 | |
paul@31 | 56 | i = 0 |
paul@31 | 57 | limit = MAX_SCANLINE * MAX_SCANPOS |
paul@31 | 58 | while i < limit: |
paul@31 | 59 | ula.update() |
paul@31 | 60 | video.update() |
paul@31 | 61 | i += 1 |
paul@40 | 62 | |
paul@31 | 63 | return video.screen |
paul@31 | 64 | |
paul@31 | 65 | class Video: |
paul@31 | 66 | |
paul@31 | 67 | """ |
paul@31 | 68 | A class representing the video circuitry. |
paul@1 | 69 | """ |
paul@1 | 70 | |
paul@31 | 71 | def __init__(self): |
paul@31 | 72 | self.screen = array("B", repeat(0, MAX_WIDTH * 3 * MAX_HEIGHT)) |
paul@31 | 73 | self.colour = BLANK |
paul@31 | 74 | self.csync = 1 |
paul@31 | 75 | self.hs = 1 |
paul@40 | 76 | self.x = 0 |
paul@40 | 77 | self.y = 0 |
paul@1 | 78 | |
paul@40 | 79 | def set_csync(self, value): |
paul@40 | 80 | if self.csync and not value: |
paul@40 | 81 | self.y = 0 |
paul@40 | 82 | self.pos = 0 |
paul@40 | 83 | self.csync = value |
paul@40 | 84 | |
paul@40 | 85 | def set_hs(self, value): |
paul@40 | 86 | if self.hs and not value: |
paul@40 | 87 | self.x = 0 |
paul@40 | 88 | self.y += 1 |
paul@40 | 89 | self.hs = value |
paul@31 | 90 | |
paul@31 | 91 | def update(self): |
paul@40 | 92 | if MIN_PIXELLINE <= self.y < MAX_PIXELLINE: |
paul@42 | 93 | if MIN_PIXELPOS + 8 <= self.x < MAX_PIXELPOS + 8: |
paul@31 | 94 | self.screen[self.pos] = self.colour[0]; self.pos += 1 |
paul@31 | 95 | self.screen[self.pos] = self.colour[1]; self.pos += 1 |
paul@31 | 96 | self.screen[self.pos] = self.colour[2]; self.pos += 1 |
paul@40 | 97 | self.x += 1 |
paul@40 | 98 | |
paul@40 | 99 | class RAM: |
paul@40 | 100 | |
paul@40 | 101 | """ |
paul@40 | 102 | A class representing the RAM circuits (IC4 to IC7). Each circuit |
paul@48 | 103 | traditionally holds 64 kilobits, with each access obtaining 1 bit from each |
paul@48 | 104 | IC, and thus two accesses being required to obtain a whole byte. Here, we |
paul@48 | 105 | model the circuits with a list of 65536 half-bytes with each bit in a |
paul@48 | 106 | half-byte representing a bit stored on a separate IC. |
paul@40 | 107 | """ |
paul@40 | 108 | |
paul@40 | 109 | def __init__(self): |
paul@40 | 110 | |
paul@40 | 111 | "Initialise the RAM circuits." |
paul@40 | 112 | |
paul@40 | 113 | self.memory = [0] * MAX_RAM |
paul@40 | 114 | self.row_address = 0 |
paul@40 | 115 | self.column_address = 0 |
paul@40 | 116 | self.data = 0 |
paul@40 | 117 | |
paul@40 | 118 | def row_select(self, address): |
paul@59 | 119 | |
paul@59 | 120 | "The operation of asserting a row 'address' via RA0...RA7." |
paul@59 | 121 | |
paul@40 | 122 | self.row_address = address |
paul@40 | 123 | |
paul@40 | 124 | def row_deselect(self): |
paul@40 | 125 | pass |
paul@40 | 126 | |
paul@40 | 127 | def column_select(self, address): |
paul@59 | 128 | |
paul@59 | 129 | "The operation of asserting a column 'address' via RA0...RA7." |
paul@59 | 130 | |
paul@40 | 131 | self.column_address = address |
paul@40 | 132 | |
paul@40 | 133 | # Read the data. |
paul@40 | 134 | |
paul@40 | 135 | self.data = self.memory[self.row_address << 8 | self.column_address] |
paul@40 | 136 | |
paul@40 | 137 | def column_deselect(self): |
paul@40 | 138 | pass |
paul@40 | 139 | |
paul@40 | 140 | # Convenience methods. |
paul@40 | 141 | |
paul@40 | 142 | def fill(self, start, end, value): |
paul@40 | 143 | for i in xrange(start, end): |
paul@40 | 144 | self.memory[i << 1] = value >> 4 |
paul@40 | 145 | self.memory[i << 1 | 0x1] = value & 0xf |
paul@29 | 146 | |
paul@66 | 147 | class ShiftRegister: |
paul@66 | 148 | |
paul@66 | 149 | """ |
paul@66 | 150 | A class representing a shift register, used for the internal state of the |
paul@66 | 151 | ULA within each 2MHz period. |
paul@66 | 152 | """ |
paul@66 | 153 | |
paul@66 | 154 | def __init__(self): |
paul@66 | 155 | self.state = [0] * 8 |
paul@66 | 156 | self.input = 0 |
paul@66 | 157 | |
paul@66 | 158 | def set_input(self, input): |
paul@66 | 159 | self.input = input |
paul@66 | 160 | |
paul@66 | 161 | def shift(self): |
paul@66 | 162 | |
paul@66 | 163 | # NOTE: This is not meant to be "nice" Python, but instead models the |
paul@66 | 164 | # NOTE: propagation of state through the latches. |
paul@66 | 165 | |
paul@66 | 166 | self.state[0], self.state[1], self.state[2], self.state[3], \ |
paul@66 | 167 | self.state[4], self.state[5], self.state[6], self.state[7] = \ |
paul@66 | 168 | self.input, self.state[0], self.state[1], self.state[2], \ |
paul@66 | 169 | self.state[3], self.state[4], self.state[5], self.state[6] |
paul@66 | 170 | |
paul@66 | 171 | def __getitem__(self, i): |
paul@66 | 172 | return self.state[i] |
paul@66 | 173 | |
paul@2 | 174 | class ULA: |
paul@2 | 175 | |
paul@31 | 176 | """ |
paul@31 | 177 | A class providing the ULA functionality. Instances of this class refer to |
paul@31 | 178 | the system memory, maintain internal state (such as information about the |
paul@31 | 179 | current screen mode), and provide outputs (such as the current pixel |
paul@31 | 180 | colour). |
paul@31 | 181 | """ |
paul@1 | 182 | |
paul@2 | 183 | modes = [ |
paul@2 | 184 | (640, 1, 32), (320, 2, 32), (160, 4, 32), # (width, depth, rows) |
paul@3 | 185 | (640, 1, 25), (320, 1, 32), (160, 2, 32), |
paul@3 | 186 | (320, 1, 25) |
paul@2 | 187 | ] |
paul@2 | 188 | |
paul@40 | 189 | def __init__(self, ram, video): |
paul@1 | 190 | |
paul@40 | 191 | "Initialise the ULA with the given 'ram' and 'video' instances." |
paul@2 | 192 | |
paul@40 | 193 | self.ram = ram |
paul@31 | 194 | self.video = video |
paul@2 | 195 | self.set_mode(6) |
paul@91 | 196 | self.palette = map(get_physical_colour, range(0, 8) * 2) |
paul@1 | 197 | |
paul@31 | 198 | self.reset() |
paul@31 | 199 | |
paul@31 | 200 | def reset(self): |
paul@31 | 201 | |
paul@31 | 202 | "Reset the ULA." |
paul@31 | 203 | |
paul@43 | 204 | # General state. |
paul@43 | 205 | |
paul@43 | 206 | self.nmi = 0 # no NMI asserted initially |
paul@43 | 207 | self.irq_vsync = 0 # no IRQ asserted initially |
paul@43 | 208 | |
paul@59 | 209 | # Communication. |
paul@59 | 210 | |
paul@59 | 211 | self.ram_address = 0 # address given to the RAM via RA0...RA7 |
paul@59 | 212 | self.data = 0 # data read from the RAM via RAM0...RAM3 |
paul@59 | 213 | self.cpu_address = 0 # address selected by the CPU via A0...A15 |
paul@59 | 214 | self.cpu_read = 0 # data read/write by the CPU selected using R/W |
paul@59 | 215 | |
paul@40 | 216 | # Internal state. |
paul@40 | 217 | |
paul@40 | 218 | self.access = 0 # counter used to determine whether a byte needs reading |
paul@42 | 219 | self.have_pixels = 0 # whether pixel data has been read |
paul@42 | 220 | self.writing_pixels = 0 # whether pixel data can be written |
paul@90 | 221 | self.pdata = [0]*8 # decoded RAM data for pixel output |
paul@40 | 222 | |
paul@66 | 223 | self.cycle = ShiftRegister() # 8-state counter within each 2MHz period |
paul@66 | 224 | |
paul@66 | 225 | self.cycle.set_input(1) # assert the input to set the first state output |
paul@66 | 226 | self.cycle.shift() |
paul@66 | 227 | self.cycle.set_input(0) # reset the input since only one state output will be active |
paul@50 | 228 | |
paul@87 | 229 | self.next_frame() |
paul@31 | 230 | |
paul@2 | 231 | def set_mode(self, mode): |
paul@1 | 232 | |
paul@2 | 233 | """ |
paul@2 | 234 | For the given 'mode', initialise the... |
paul@1 | 235 | |
paul@2 | 236 | * width in pixels |
paul@2 | 237 | * colour depth in bits per pixel |
paul@2 | 238 | * number of character rows |
paul@2 | 239 | * character row size in bytes |
paul@2 | 240 | * screen size in bytes |
paul@2 | 241 | * default screen start address |
paul@2 | 242 | * horizontal pixel scaling factor |
paul@88 | 243 | * row height in pixels |
paul@88 | 244 | * display height in pixels |
paul@31 | 245 | |
paul@31 | 246 | The ULA should be reset after a mode switch in order to cleanly display |
paul@31 | 247 | a full screen. |
paul@2 | 248 | """ |
paul@1 | 249 | |
paul@3 | 250 | self.width, self.depth, rows = self.modes[mode] |
paul@3 | 251 | |
paul@31 | 252 | columns = (self.width * self.depth) / 8 # bits read -> bytes read |
paul@40 | 253 | self.access_frequency = 80 / columns # cycle frequency for reading bytes |
paul@31 | 254 | row_size = columns * LINES_PER_ROW |
paul@2 | 255 | |
paul@3 | 256 | # Memory access configuration. |
paul@4 | 257 | # Note the limitation on positioning the screen start. |
paul@3 | 258 | |
paul@4 | 259 | screen_size = row_size * rows |
paul@4 | 260 | self.screen_start = (SCREEN_LIMIT - screen_size) & 0xff00 |
paul@4 | 261 | self.screen_size = SCREEN_LIMIT - self.screen_start |
paul@3 | 262 | |
paul@3 | 263 | # Scanline configuration. |
paul@1 | 264 | |
paul@22 | 265 | self.xscale = MAX_WIDTH / self.width # pixel width in display pixels |
paul@88 | 266 | self.row_height = MAX_HEIGHT / rows # row height in display pixels |
paul@88 | 267 | self.display_height = rows * self.row_height # display height in pixels |
paul@3 | 268 | |
paul@40 | 269 | def vsync(self, value=0): |
paul@40 | 270 | |
paul@40 | 271 | "Signal the start of a frame." |
paul@40 | 272 | |
paul@40 | 273 | self.csync = value |
paul@40 | 274 | self.video.set_csync(value) |
paul@40 | 275 | |
paul@40 | 276 | def hsync(self, value=0): |
paul@40 | 277 | |
paul@40 | 278 | "Signal the end of a scanline." |
paul@40 | 279 | |
paul@40 | 280 | self.hs = value |
paul@40 | 281 | self.video.set_hs(value) |
paul@40 | 282 | |
paul@87 | 283 | def next_frame(self): |
paul@2 | 284 | |
paul@2 | 285 | "Signal the start of a frame." |
paul@1 | 286 | |
paul@2 | 287 | self.line_start = self.address = self.screen_start |
paul@5 | 288 | self.line = self.line_start % LINES_PER_ROW |
paul@31 | 289 | self.y = 0 |
paul@40 | 290 | self.x = 0 |
paul@2 | 291 | |
paul@87 | 292 | def next_horizontal(self): |
paul@87 | 293 | |
paul@87 | 294 | "Visit the next horizontal position." |
paul@87 | 295 | |
paul@87 | 296 | self.address += LINES_PER_ROW |
paul@87 | 297 | self.wrap_address() |
paul@87 | 298 | |
paul@87 | 299 | def next_vertical(self): |
paul@1 | 300 | |
paul@40 | 301 | "Reset horizontal state within the active region of the frame." |
paul@31 | 302 | |
paul@31 | 303 | self.y += 1 |
paul@40 | 304 | self.x = 0 |
paul@40 | 305 | |
paul@40 | 306 | if not self.inside_frame(): |
paul@40 | 307 | return |
paul@2 | 308 | |
paul@2 | 309 | self.line += 1 |
paul@2 | 310 | |
paul@2 | 311 | # After the end of the last line in a row, the address should already |
paul@2 | 312 | # have been positioned on the last line of the next column. |
paul@1 | 313 | |
paul@88 | 314 | if self.line == self.row_height: |
paul@88 | 315 | self.address -= LINES_PER_ROW - 1 |
paul@88 | 316 | self.wrap_address() |
paul@88 | 317 | self.line = 0 |
paul@88 | 318 | |
paul@88 | 319 | # Support spacing between character rows. |
paul@88 | 320 | |
paul@88 | 321 | elif not self.in_line(): |
paul@88 | 322 | return |
paul@88 | 323 | |
paul@88 | 324 | # If not on a row boundary, move to the next line. Here, the address |
paul@88 | 325 | # needs bringing back to the previous character row. |
paul@88 | 326 | |
paul@2 | 327 | else: |
paul@88 | 328 | self.address = self.line_start + 1 |
paul@2 | 329 | self.wrap_address() |
paul@1 | 330 | |
paul@88 | 331 | # Record the position of the start of the pixel row. |
paul@3 | 332 | |
paul@3 | 333 | self.line_start = self.address |
paul@1 | 334 | |
paul@88 | 335 | def in_line(self): return self.line < LINES_PER_ROW |
paul@88 | 336 | def in_frame(self): return MIN_PIXELLINE <= self.y < (MIN_PIXELLINE + self.display_height) |
paul@88 | 337 | def inside_frame(self): return MIN_PIXELLINE < self.y < (MIN_PIXELLINE + self.display_height) |
paul@42 | 338 | def read_pixels(self): return MIN_PIXELPOS <= self.x < MAX_PIXELPOS and self.in_frame() |
paul@31 | 339 | |
paul@31 | 340 | def update(self): |
paul@1 | 341 | |
paul@2 | 342 | """ |
paul@40 | 343 | Update the state of the ULA for each clock cycle. This involves updating |
paul@40 | 344 | the pixel colour by reading from the pixel buffer. |
paul@2 | 345 | """ |
paul@2 | 346 | |
paul@40 | 347 | # Detect the end of the scanline. |
paul@40 | 348 | |
paul@40 | 349 | if self.x == MAX_SCANPOS: |
paul@87 | 350 | self.next_vertical() |
paul@40 | 351 | |
paul@40 | 352 | # Detect the end of the frame. |
paul@40 | 353 | |
paul@40 | 354 | if self.y == MAX_SCANLINE: |
paul@87 | 355 | self.next_frame() |
paul@40 | 356 | |
paul@40 | 357 | |
paul@40 | 358 | |
paul@40 | 359 | # Clock management. |
paul@40 | 360 | |
paul@88 | 361 | would_access_ram = self.access == 0 and self.read_pixels() and self.in_line() |
paul@86 | 362 | access_ram = not self.nmi and would_access_ram |
paul@40 | 363 | |
paul@40 | 364 | # Set row address (for ULA access only). |
paul@40 | 365 | |
paul@50 | 366 | if self.cycle[0]: |
paul@40 | 367 | |
paul@59 | 368 | # Either assert a required address or propagate the CPU address. |
paul@40 | 369 | |
paul@40 | 370 | if access_ram: |
paul@59 | 371 | self.init_row_address(self.address) |
paul@59 | 372 | else: |
paul@59 | 373 | self.init_row_address(self.cpu_address) |
paul@40 | 374 | |
paul@42 | 375 | # Initialise the pixel buffer if appropriate. |
paul@42 | 376 | |
paul@42 | 377 | if not self.writing_pixels and self.have_pixels: |
paul@42 | 378 | self.buffer_index = 0 |
paul@42 | 379 | self.writing_pixels = 1 |
paul@42 | 380 | |
paul@40 | 381 | # Latch row address, set column address (for ULA access only). |
paul@40 | 382 | |
paul@50 | 383 | elif self.cycle[1]: |
paul@40 | 384 | |
paul@59 | 385 | # Select an address needed by the ULA or CPU. |
paul@59 | 386 | |
paul@59 | 387 | self.ram.row_select(self.ram_address) |
paul@59 | 388 | |
paul@59 | 389 | # Either assert a required address or propagate the CPU address. |
paul@31 | 390 | |
paul@40 | 391 | if access_ram: |
paul@59 | 392 | self.init_column_address(self.address, 0) |
paul@59 | 393 | else: |
paul@59 | 394 | self.init_column_address(self.cpu_address, 0) |
paul@40 | 395 | |
paul@40 | 396 | # Latch column address. |
paul@40 | 397 | |
paul@50 | 398 | elif self.cycle[2]: |
paul@40 | 399 | |
paul@59 | 400 | # Select an address needed by the ULA or CPU. |
paul@31 | 401 | |
paul@59 | 402 | self.ram.column_select(self.ram_address) |
paul@40 | 403 | |
paul@40 | 404 | # Read 4 bits (for ULA access only). |
paul@40 | 405 | # NOTE: Perhaps map alternate bits, not half-bytes. |
paul@40 | 406 | |
paul@50 | 407 | elif self.cycle[3]: |
paul@40 | 408 | |
paul@59 | 409 | # Either read from a required address or transfer CPU data. |
paul@40 | 410 | |
paul@40 | 411 | if access_ram: |
paul@40 | 412 | self.data = self.ram.data << 4 |
paul@59 | 413 | else: |
paul@59 | 414 | self.cpu_transfer_high() |
paul@40 | 415 | |
paul@40 | 416 | # Set column address (for ULA access only). |
paul@40 | 417 | |
paul@50 | 418 | elif self.cycle[4]: |
paul@40 | 419 | self.ram.column_deselect() |
paul@31 | 420 | |
paul@59 | 421 | # Either assert a required address or propagate the CPU address. |
paul@40 | 422 | |
paul@40 | 423 | if access_ram: |
paul@59 | 424 | self.init_column_address(self.address, 1) |
paul@59 | 425 | else: |
paul@59 | 426 | self.init_column_address(self.cpu_address, 1) |
paul@40 | 427 | |
paul@40 | 428 | # Latch column address. |
paul@40 | 429 | |
paul@50 | 430 | elif self.cycle[5]: |
paul@40 | 431 | |
paul@59 | 432 | # Select an address needed by the ULA or CPU. |
paul@40 | 433 | |
paul@59 | 434 | self.ram.column_select(self.ram_address) |
paul@31 | 435 | |
paul@40 | 436 | # Read 4 bits (for ULA access only). |
paul@40 | 437 | # NOTE: Perhaps map alternate bits, not half-bytes. |
paul@40 | 438 | |
paul@50 | 439 | elif self.cycle[6]: |
paul@40 | 440 | |
paul@59 | 441 | # Either read from a required address or transfer CPU data. |
paul@40 | 442 | |
paul@40 | 443 | if access_ram: |
paul@40 | 444 | self.data = self.data | self.ram.data |
paul@42 | 445 | self.have_pixels = 1 |
paul@90 | 446 | |
paul@90 | 447 | # Rearrange the byte value. |
paul@90 | 448 | |
paul@90 | 449 | self.pdata = decode(self.data, self.depth) |
paul@86 | 450 | else: |
paul@86 | 451 | self.cpu_transfer_low() |
paul@40 | 452 | |
paul@86 | 453 | # Advance to the next column even if an NMI is asserted. |
paul@40 | 454 | |
paul@86 | 455 | if would_access_ram: |
paul@87 | 456 | self.next_horizontal() |
paul@40 | 457 | |
paul@40 | 458 | # Reset addresses. |
paul@31 | 459 | |
paul@50 | 460 | elif self.cycle[7]: |
paul@40 | 461 | self.ram.column_deselect() |
paul@40 | 462 | self.ram.row_deselect() |
paul@40 | 463 | |
paul@40 | 464 | # Update the RAM access controller. |
paul@40 | 465 | |
paul@40 | 466 | self.access = (self.access + 1) % self.access_frequency |
paul@40 | 467 | |
paul@66 | 468 | # Update the state of the device. |
paul@66 | 469 | |
paul@66 | 470 | self.cycle.set_input(self.cycle[7]) |
paul@66 | 471 | self.cycle.shift() |
paul@66 | 472 | |
paul@40 | 473 | |
paul@40 | 474 | |
paul@40 | 475 | # Video signalling. |
paul@40 | 476 | |
paul@40 | 477 | # Detect any sync conditions. |
paul@31 | 478 | |
paul@40 | 479 | if self.x == 0: |
paul@40 | 480 | self.hsync() |
paul@40 | 481 | if self.y == 0: |
paul@40 | 482 | self.vsync() |
paul@43 | 483 | self.irq_vsync = 0 |
paul@43 | 484 | elif self.y == MAX_PIXELLINE: |
paul@43 | 485 | self.irq_vsync = 1 |
paul@40 | 486 | |
paul@40 | 487 | # Detect the end of hsync. |
paul@31 | 488 | |
paul@40 | 489 | elif self.x == MAX_HSYNC: |
paul@40 | 490 | self.hsync(1) |
paul@40 | 491 | |
paul@40 | 492 | # Detect the end of vsync. |
paul@40 | 493 | |
paul@40 | 494 | elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2: |
paul@40 | 495 | self.vsync(1) |
paul@40 | 496 | |
paul@40 | 497 | |
paul@85 | 498 | self.x += 1 |
paul@85 | 499 | |
paul@40 | 500 | |
paul@40 | 501 | # Pixel production. |
paul@31 | 502 | |
paul@3 | 503 | # Detect spacing between character rows. |
paul@3 | 504 | |
paul@88 | 505 | if not self.writing_pixels or not self.in_line(): |
paul@31 | 506 | self.video.colour = BLANK |
paul@3 | 507 | |
paul@31 | 508 | # For pixels within the frame, obtain and output the value. |
paul@31 | 509 | |
paul@31 | 510 | else: |
paul@90 | 511 | self.video.colour = self.get_pixel() |
paul@1 | 512 | |
paul@31 | 513 | # Scale pixels horizontally, only accessing the next pixel value |
paul@31 | 514 | # after the required number of scan positions. |
paul@22 | 515 | |
paul@85 | 516 | if self.x % self.xscale == 0: |
paul@90 | 517 | self.buffer_index += self.depth |
paul@31 | 518 | |
paul@83 | 519 | # Finish writing pixels. |
paul@22 | 520 | |
paul@85 | 521 | if self.x % PIXEL_POSITIONS == 0: |
paul@83 | 522 | self.writing_pixels = 0 |
paul@2 | 523 | |
paul@90 | 524 | def get_pixel(self): |
paul@1 | 525 | |
paul@2 | 526 | """ |
paul@90 | 527 | Return the current pixel by translating memory content for the current |
paul@2 | 528 | mode. |
paul@2 | 529 | """ |
paul@1 | 530 | |
paul@91 | 531 | return self.palette[value_of_bits(self.pdata[self.buffer_index:self.buffer_index+self.depth])] |
paul@2 | 532 | |
paul@2 | 533 | def wrap_address(self): |
paul@2 | 534 | if self.address >= SCREEN_LIMIT: |
paul@2 | 535 | self.address -= self.screen_size |
paul@1 | 536 | |
paul@59 | 537 | def init_row_address(self, address): |
paul@59 | 538 | self.ram_address = (address & 0xff80) >> 7 |
paul@59 | 539 | |
paul@59 | 540 | def init_column_address(self, address, offset): |
paul@59 | 541 | self.ram_address = (address & 0x7f) << 1 | offset |
paul@59 | 542 | |
paul@59 | 543 | def cpu_transfer_high(self): |
paul@59 | 544 | if self.cpu_read: |
paul@59 | 545 | self.cpu_data = self.ram.data << 4 |
paul@59 | 546 | |
paul@59 | 547 | def cpu_transfer_low(self): |
paul@59 | 548 | if self.cpu_read: |
paul@59 | 549 | self.cpu_data = self.data | self.ram.data |
paul@59 | 550 | |
paul@89 | 551 | def value_of_bits(bits): |
paul@89 | 552 | |
paul@89 | 553 | "Convert the sequence of 'bits' into a value." |
paul@89 | 554 | |
paul@89 | 555 | value = 0 |
paul@89 | 556 | for bit in bits: |
paul@89 | 557 | value *= 2 |
paul@89 | 558 | value += bit and 1 or 0 |
paul@89 | 559 | return value |
paul@89 | 560 | |
paul@1 | 561 | def get_physical_colour(value): |
paul@1 | 562 | |
paul@1 | 563 | """ |
paul@1 | 564 | Return the physical colour as an RGB triple for the given 'value'. |
paul@1 | 565 | """ |
paul@1 | 566 | |
paul@1 | 567 | return value & 1, value >> 1 & 1, value >> 2 & 1 |
paul@1 | 568 | |
paul@1 | 569 | def decode(value, depth): |
paul@1 | 570 | |
paul@1 | 571 | """ |
paul@1 | 572 | Decode the given byte 'value' according to the 'depth' in bits per pixel, |
paul@1 | 573 | returning a sequence of pixel values. |
paul@1 | 574 | """ |
paul@1 | 575 | |
paul@1 | 576 | if depth == 1: |
paul@1 | 577 | return (value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 4 & 1, |
paul@1 | 578 | value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1) |
paul@1 | 579 | elif depth == 2: |
paul@89 | 580 | return (value >> 7, value >> 3 & 1, value >> 6 & 1, value >> 2 & 1, |
paul@89 | 581 | value >> 5 & 1, value >> 1 & 1, value >> 4 & 1, value & 1) |
paul@1 | 582 | elif depth == 4: |
paul@89 | 583 | return (value >> 7, value >> 5 & 1, value >> 3 & 1, value >> 1 & 1, |
paul@89 | 584 | value >> 6 & 1, value >> 4 & 1, value >> 2 & 1, value & 1) |
paul@1 | 585 | else: |
paul@1 | 586 | raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth |
paul@1 | 587 | |
paul@1 | 588 | # Convenience functions. |
paul@1 | 589 | |
paul@1 | 590 | def encode(values, depth): |
paul@1 | 591 | |
paul@1 | 592 | """ |
paul@1 | 593 | Encode the given 'values' according to the 'depth' in bits per pixel, |
paul@1 | 594 | returning a byte value for the pixels. |
paul@1 | 595 | """ |
paul@1 | 596 | |
paul@1 | 597 | result = 0 |
paul@1 | 598 | |
paul@1 | 599 | if depth == 1: |
paul@1 | 600 | for value in values: |
paul@1 | 601 | result = result << 1 | (value & 1) |
paul@1 | 602 | elif depth == 2: |
paul@1 | 603 | for value in values: |
paul@1 | 604 | result = result << 1 | (value & 2) << 3 | (value & 1) |
paul@1 | 605 | elif depth == 4: |
paul@1 | 606 | for value in values: |
paul@1 | 607 | result = result << 1 | (value & 8) << 3 | (value & 4) << 2 | (value & 2) << 1 | (value & 1) |
paul@1 | 608 | else: |
paul@1 | 609 | raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth |
paul@1 | 610 | |
paul@1 | 611 | return result |
paul@1 | 612 | |
paul@11 | 613 | def get_ula(): |
paul@11 | 614 | |
paul@31 | 615 | "Return a ULA initialised with a memory array and video." |
paul@31 | 616 | |
paul@40 | 617 | return ULA(get_ram(), get_video()) |
paul@11 | 618 | |
paul@31 | 619 | def get_video(): |
paul@31 | 620 | |
paul@31 | 621 | "Return a video circuit." |
paul@31 | 622 | |
paul@31 | 623 | return Video() |
paul@11 | 624 | |
paul@40 | 625 | def get_ram(): |
paul@10 | 626 | |
paul@40 | 627 | "Return an instance representing the computer's RAM hardware." |
paul@7 | 628 | |
paul@40 | 629 | return RAM() |
paul@1 | 630 | |
paul@7 | 631 | # Test program providing coverage (necessary for compilers like Shedskin). |
paul@7 | 632 | |
paul@7 | 633 | if __name__ == "__main__": |
paul@11 | 634 | ula = get_ula() |
paul@7 | 635 | ula.set_mode(2) |
paul@40 | 636 | ula.reset() |
paul@40 | 637 | ula.ram.fill(0x5800 - 320, 0x8000, encode((2, 7), 4)) |
paul@7 | 638 | |
paul@7 | 639 | # Make a simple two-dimensional array of tuples (three-dimensional in pygame |
paul@7 | 640 | # terminology). |
paul@7 | 641 | |
paul@29 | 642 | a = update(ula) |
paul@7 | 643 | |
paul@1 | 644 | # vim: tabstop=4 expandtab shiftwidth=4 |