102:37c6315ecb87
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2016-06-21 |
Paul Boddie |
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Removed the width instance attribute. |
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ula.py
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101:4658aa28f367
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2016-06-21 |
Paul Boddie |
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Moved address preparation onto negative edges and data acquisition onto positive
edges, using the have_pixels variable to indicate if a read operation needs
completing at the start of a new 2MHz period.
Fixed various comments and docstrings. |
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ULA.txt ula.py
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100:13c8893af8c7
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2016-06-21 |
Paul Boddie |
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Shifted the timing states so that cycle 0 is aligned with the positive edge of
any 2MHz CPU clock.
Made methods for various access timing tests and replaced the distinct access
variable with a test against the horizontal pixel counter (effectively using it
as a 2MHz cycle counter). |
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ULA.txt ula.py
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99:87b0ccdb9bc4
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2016-06-21 |
Paul Boddie |
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Refined and expanded the RAM access timings, moving data transfers to the
negative edge handler. |
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ULA.txt ula.py
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98:05ee520ae9d1
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2016-06-20 |
Paul Boddie |
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Renamed address to pixel_address. |
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ula.py
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97:5101ef5b3e3a
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2016-06-20 |
Paul Boddie |
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Added initial CPU abstraction support together with read/write selection and
PHI OUT clock signal generation. |
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ULA.txt ula.py
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96:c0f8098f982f
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2016-06-20 |
Paul Boddie |
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Made the next_vertical control-flow more hierarchical. |
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ula.py
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95:e116a929dcdf
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2016-06-20 |
Paul Boddie |
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Introduced positive and negative signal transition update methods in order to
separate state transitions from other operations, simplifying the pixel cycle
management slightly. |
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ula.py
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94:59d7fe6a9ba0
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2016-06-20 |
Paul Boddie |
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Tidied, introducing a write_pixels function, removing PIXEL_POSITIONS. |
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ula.py
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93:ea19ad85988b
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2016-06-20 |
Paul Boddie |
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Fixed and tidied up pixel production, employing the general state counter for
pixel output and a specific state counter to track pixel scaling.
Replaced the shift register abstraction with plain integer use.
Made the rotate function more general. |
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ula.py
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