1.1 --- a/ULA.txt Tue Jun 21 14:34:11 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 16:06:47 2016 +0200
1.3 @@ -52,21 +52,21 @@
1.4 2 MHz cycle: 0 1 ...
1.5 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.6 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
1.7 - ~RAS: --\___________/---\___________/- ...
1.8 - ~CAS: ----\___/-\___/-----\___/-\___/- ...
1.9 - A B C A B C ...
1.10 - F S F S ...
1.11 - a b c a b c ...
1.12 - f s f s ...
1.13 + ~RAS: /---\___________/---\___________ ...
1.14 + ~CAS: /-----\___/-\___/-----\___/-\___ ...
1.15 + A B C A B C ...
1.16 + F S F S ...
1.17 + a b c a b c ...
1.18 + s f s f ...
1.19
1.20 - ~WE: ......W ...
1.21 - PHI OUT: ______________/---------------\ ...
1.22 - CPU (RAM): D L ...
1.23 - RnW: R ...
1.24 + ~WE: ......W ...
1.25 + PHI OUT: \_______________/--------------- ...
1.26 + CPU (RAM): L D ...
1.27 + RnW: R ...
1.28
1.29 - PHI OUT: ______/-------\_______/-------\ ...
1.30 - CPU (ROM): D L D L ...
1.31 - RnW: R R ...
1.32 + PHI OUT: \_______/-------\_______/------- ...
1.33 + CPU (ROM): L D L D ...
1.34 + RnW: R R ...
1.35
1.36 Here, "A" and "B" respectively indicate the row and first column addresses
1.37 being latched into the RAM (on a negative edge for ~RAS and ~CAS