1.1 --- a/ula.py Tue Jun 21 16:06:47 2016 +0200
1.2 +++ b/ula.py Tue Jun 21 20:18:37 2016 +0200
1.3 @@ -375,33 +375,32 @@
1.4
1.5 def posedge_ram(self):
1.6
1.7 - "RAM signalling."
1.8 + """
1.9 + RAM signalling.
1.10 +
1.11 + States handled: * _ * * _ * * _
1.12 + """
1.13
1.14 # Clock management.
1.15
1.16 - # Reset addresses.
1.17 + # Read 4 bits (for RAM access only).
1.18
1.19 if self.cycle == 1:
1.20 +
1.21 + # Reset addresses.
1.22 +
1.23 self.ram.column_deselect()
1.24 self.ram.row_deselect()
1.25
1.26 - # Read the CPU address, if appropriate.
1.27 -
1.28 - if not self.access_ram():
1.29 - self.cpu_update_clock()
1.30 -
1.31 - # Set row address (for ULA access only).
1.32 -
1.33 - elif self.cycle == 2:
1.34 + # Either read from a required address or transfer CPU data.
1.35
1.36 - # Either assert a required address or propagate the CPU address.
1.37 + if self.have_pixels:
1.38 + self.data = (self.data & 0xf0) | self.ram.data
1.39 + else:
1.40 + self.cpu_update_clock()
1.41 + self.cpu_transfer_low()
1.42
1.43 - if self.access_ram():
1.44 - self.init_row_address(self.pixel_address)
1.45 - else:
1.46 - self.init_row_address(self.cpu_address)
1.47 -
1.48 - # Latch row address, set column address (for ULA access only).
1.49 + # Latch row address.
1.50
1.51 elif self.cycle == 4:
1.52
1.53 @@ -409,13 +408,6 @@
1.54
1.55 self.ram.row_select(self.ram_address)
1.56
1.57 - # Either assert a required address or propagate the CPU address.
1.58 -
1.59 - if self.access_ram():
1.60 - self.init_column_address(self.pixel_address, 0)
1.61 - else:
1.62 - self.init_column_address(self.cpu_address, 0)
1.63 -
1.64 # Latch column address.
1.65
1.66 elif self.cycle == 8:
1.67 @@ -431,19 +423,20 @@
1.68 else:
1.69 self.cpu_transfer_select()
1.70
1.71 - # Cycle handled in negedge.
1.72 -
1.73 - # Set column address (for ULA access only).
1.74 + # Read 4 bits (for RAM access only).
1.75
1.76 elif self.cycle == 32:
1.77 +
1.78 + # Prepare to latch column address.
1.79 +
1.80 self.ram.column_deselect()
1.81
1.82 - # Either assert a required address or propagate the CPU address.
1.83 + # Either read from a required address or transfer CPU data.
1.84
1.85 if self.access_ram():
1.86 - self.init_column_address(self.pixel_address, 1)
1.87 + self.data = self.ram.data << 4
1.88 else:
1.89 - self.init_column_address(self.cpu_address, 1)
1.90 + self.cpu_transfer_high()
1.91
1.92 # Latch column address.
1.93
1.94 @@ -453,15 +446,6 @@
1.95
1.96 self.ram.column_select(self.ram_address)
1.97
1.98 - # Read 4 bits (for ULA access only).
1.99 -
1.100 - elif self.cycle == 128:
1.101 -
1.102 - # Advance to the next column even if an NMI is asserted.
1.103 -
1.104 - if self.would_access_ram():
1.105 - self.next_horizontal()
1.106 -
1.107 def posedge_pixel(self):
1.108
1.109 "Pixel production."
1.110 @@ -487,7 +471,7 @@
1.111 """
1.112 Update the state of the device.
1.113
1.114 - Cycles handled: * _ _ _ * _ _ *
1.115 + States handled: * * * _ _ * _ *
1.116 """
1.117
1.118 # Clock management.
1.119 @@ -500,28 +484,52 @@
1.120 self.pcycle = 1
1.121 self.have_pixels = 0
1.122
1.123 - # Read 4 bits (for ULA access only).
1.124 + # Set row address (for RAM access only).
1.125
1.126 - elif self.cycle == 16:
1.127 + elif self.cycle == 2:
1.128
1.129 - # Either read from a required address or transfer CPU data.
1.130 + # Either assert a required address or propagate the CPU address.
1.131
1.132 if self.access_ram():
1.133 - self.data = self.ram.data << 4
1.134 + self.init_row_address(self.pixel_address)
1.135 + else:
1.136 + self.init_row_address(self.cpu_address)
1.137 +
1.138 + # Latch row address, set column address (for RAM access only).
1.139 +
1.140 + elif self.cycle == 4:
1.141 +
1.142 + # Either assert a required address or propagate the CPU address.
1.143 +
1.144 + if self.access_ram():
1.145 + self.init_column_address(self.pixel_address, 0)
1.146 else:
1.147 - self.cpu_transfer_high()
1.148 + self.init_column_address(self.cpu_address, 0)
1.149 +
1.150 + # Set column address (for RAM access only).
1.151 +
1.152 + elif self.cycle == 32:
1.153
1.154 - # Read 4 bits (for ULA access only).
1.155 + # Either assert a required address or propagate the CPU address.
1.156 +
1.157 + if self.access_ram():
1.158 + self.init_column_address(self.pixel_address, 1)
1.159 + else:
1.160 + self.init_column_address(self.cpu_address, 1)
1.161 +
1.162 + # Update addresses.
1.163
1.164 elif self.cycle == 128:
1.165
1.166 - # Either read from a required address or transfer CPU data.
1.167 + # Advance to the next column even if an NMI is asserted.
1.168 +
1.169 + if self.would_access_ram():
1.170 + self.next_horizontal()
1.171 +
1.172 + # If the ULA accessed RAM, indicate that a read needs completing.
1.173
1.174 if self.access_ram():
1.175 - self.data = self.data | self.ram.data
1.176 self.have_pixels = 1
1.177 - else:
1.178 - self.cpu_transfer_low()
1.179
1.180 # Start a new cycle.
1.181