1.1 --- a/ULA.txt Mon Jun 20 21:32:22 2016 +0200
1.2 +++ b/ULA.txt Mon Jun 20 23:17:48 2016 +0200
1.3 @@ -57,6 +57,11 @@
1.4 F S F S ...
1.5 a b c a b c ...
1.6
1.7 + ~WE: ......W ...
1.8 + PHI OUT: ______________/---------------\ ...
1.9 + CPU: D L ...
1.10 + RnW: R ...
1.11 +
1.12 Here, "A" and "B" respectively indicate the row and first column addresses
1.13 being latched into the RAM (on a negative edge for ~RAS and ~CAS
1.14 respectively), and "C" indicates the second column address being latched into
1.15 @@ -64,6 +69,15 @@
1.16 "S" respectively, and the row and column addresses must be made available at
1.17 "a" and "b" (and "c") respectively at the latest.
1.18
1.19 +For the CPU, "L" indicates the point at which an address is taken from the CPU
1.20 +address bus, on a negative edge of PHI OUT, with "D" being the point at which
1.21 +data may either be read or be asserted for writing, on a positive edge of PHI
1.22 +OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
1.23 +for writing or high for reading, and thus propagates RnW from the CPU, this
1.24 +would need to be done before data would be retrieved and, according to the
1.25 +TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
1.26 +brought low.
1.27 +
1.28 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
1.29 address access time of 90ns (maximum), which appears to mean that
1.30 approximately two 16MHz cycles after the row address is latched, and one and a