1.1 --- a/ULA.txt Mon Jun 20 23:40:11 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 14:34:11 2016 +0200
1.3 @@ -48,26 +48,33 @@
1.4 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
1.5 patterns corresponding to 16MHz cycles are required:
1.6
1.7 - Time (ns): 0-------------- 500------------ ...
1.8 - 2 MHz cycle: 0 1 ...
1.9 - 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.10 - ~RAS: 0 1 0 1 ...
1.11 - ~CAS: 0 1 0 1 0 1 0 1 ...
1.12 - A B C A B C ...
1.13 - F S F S ...
1.14 - a b c a b c ...
1.15 + Time (ns): 0-------------- 500------------- ...
1.16 + 2 MHz cycle: 0 1 ...
1.17 + 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
1.18 + /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
1.19 + ~RAS: --\___________/---\___________/- ...
1.20 + ~CAS: ----\___/-\___/-----\___/-\___/- ...
1.21 + A B C A B C ...
1.22 + F S F S ...
1.23 + a b c a b c ...
1.24 + f s f s ...
1.25
1.26 - ~WE: ......W ...
1.27 - PHI OUT: ______________/---------------\ ...
1.28 - CPU: D L ...
1.29 - RnW: R ...
1.30 + ~WE: ......W ...
1.31 + PHI OUT: ______________/---------------\ ...
1.32 + CPU (RAM): D L ...
1.33 + RnW: R ...
1.34 +
1.35 + PHI OUT: ______/-------\_______/-------\ ...
1.36 + CPU (ROM): D L D L ...
1.37 + RnW: R R ...
1.38
1.39 Here, "A" and "B" respectively indicate the row and first column addresses
1.40 being latched into the RAM (on a negative edge for ~RAS and ~CAS
1.41 respectively), and "C" indicates the second column address being latched into
1.42 the RAM. Presumably, the first and second half-bytes can be read at "F" and
1.43 "S" respectively, and the row and column addresses must be made available at
1.44 -"a" and "b" (and "c") respectively at the latest.
1.45 +"a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
1.46 +"s" for the first and second half-bytes respectively.
1.47
1.48 For the CPU, "L" indicates the point at which an address is taken from the CPU
1.49 address bus, on a negative edge of PHI OUT, with "D" being the point at which
1.50 @@ -79,9 +86,11 @@
1.51 brought low.
1.52
1.53 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
1.54 -address access time of 90ns (maximum), which appears to mean that
1.55 -approximately two 16MHz cycles after the row address is latched, and one and a
1.56 -half cycles after the column address is latched, the data becomes available.
1.57 +address access time of 90ns (maximum), which appears to mean that ~RAS must be
1.58 +held low for at least 150ns and that ~CAS must be held low for at least 90ns
1.59 +before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
1.60 +cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
1.61 +is 1.5 cycles.
1.62
1.63 Note that the Service Manual refers to the negative edge of RAS and CAS, but
1.64 the datasheet for the similar TM4164EC4 product shows latching on the negative