1.1 --- a/ULA.txt Tue Jun 21 23:20:26 2016 +0200
1.2 +++ b/ULA.txt Tue Jun 21 23:22:33 2016 +0200
1.3 @@ -109,7 +109,10 @@
1.4 The CPU, when accessing the RAM alone, apparently does not make use of the
1.5 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
1.6 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
1.7 -accessing ROM (and potentially sideways RAM).
1.8 +accessing ROM (and potentially sideways RAM). The principal limitation is the
1.9 +amount of time needed between issuing an address and receiving an entire byte
1.10 +from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
1.11 +4 cycles that would be required for 2MHz operation.
1.12
1.13 See: Acorn Electron Advanced User Guide
1.14 See: Acorn Electron Service Manual
1.15 @@ -597,6 +600,9 @@
1.16 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
1.17 doubled, but the CPU bandwidth increase is still significant.
1.18
1.19 +Unfortunately, the mechanism for accessing the RAM is too slow to provide data
1.20 +within the time constraints of 2MHz operation.
1.21 +
1.22 Enhancement: Region Blanking
1.23 ----------------------------
1.24