1.1 --- a/ULA.txt Sun Jan 29 20:40:59 2012 +0100
1.2 +++ b/ULA.txt Sun Jan 29 21:50:13 2012 +0100
1.3 @@ -13,7 +13,11 @@
1.4
1.5 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
1.6 each providing two bits of each byte) using two cycles within the 500ns period
1.7 -of the 2MHz clock to complete each access operation.
1.8 +of the 2MHz clock to complete each access operation. Since the CPU and ULA
1.9 +have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
1.10 +effectively run at 1MHz (since every other 500ns period involves the ULA
1.11 +accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
1.12 +frequency is divided by the ULA (IC1) depending on the screen mode in use.
1.13
1.14 See: Acorn Electron Service Manual
1.15