1 Principal Design and Feature Constraints
2 ----------------------------------------
3
4 The features of the ULA are limited by the amount of time and resources that
5 can be allocated to each activity necessary to support such features given the
6 fundamental obligations of the unit. Maintaining a screen display based on the
7 contents of RAM itself requires the ULA to have exclusive access to such
8 hardware resources for a significant period of time. Whilst other elements of
9 the ULA can in principle run in parallel with this activity, they cannot also
10 access the RAM. Consequently, other features that might use the RAM must
11 accept a reduced allocation of that resource in comparison to a hypothetical
12 architecture where concurrent RAM access is possible.
13
14 Thus, the principal constraint for many features is bandwidth. The duration of
15 access to hardware resources is one aspect of this; the rate at which such
16 resources can be accessed is another. For example, the RAM is not fast enough
17 to support access more frequently than one byte per 2MHz cycle, and for screen
18 modes involving 80 bytes of screen data per scanline, there are no free cycles
19 for anything other than the production of pixel output during the active
20 scanline periods.
21
22 Timing
23 ------
24
25 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
26 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
27 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
28 312 ~= 128 cycles). This is consistent with the observation that each scanline
29 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
30 out of 64 microseconds in each scanline.
31
32 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
33 each providing two bits of each byte) using two cycles within the 500ns period
34 of the 2MHz clock to complete each access operation. Since the CPU and ULA
35 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
36 effectively run at 1MHz (since every other 500ns period involves the ULA
37 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
38 frequency is divided by the ULA (IC1) depending on the screen mode in use.
39
40 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
41 patterns corresponding to 16MHz cycles are required:
42
43 Time (ns): 0-------------- 500------------ ...
44 2 MHz cycle: 0 1 ...
45 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
46 ~RAS: 0 1 0 1 ...
47 ~CAS: 0 1 0 1 0 1 0 1 ...
48 A B B A B B ...
49 F S F S ...
50 a b b a b b ...
51
52 Here, "A" indicates the row and column addresses being latched into the RAM
53 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
54 second column address being latched into the RAM. Presumably, the first and
55 second half-bytes can be read at "F" and "S" respectively, and the row and
56 column addresses must be made available at "a" and "b" respectively at the
57 latest.
58
59 Note that the Service Manual refers to the negative edge of RAS and CAS, but
60 the datasheet for the similar TM4164EC4 product shows latching on the negative
61 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
62 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
63 "page mode" provides the appropriate behaviour for that particular product.
64
65 Video Timing
66 ------------
67
68 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
69 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
70 (including the "colour burst"), and 1.65µs for the "front porch", totalling
71 12.05µs and thus leaving 51.95µs for the active video signal for each
72 scanline. As the Service Manual suggests in the oscilloscope traces, the
73 display information is transmitted more or less centred within the active
74 video period since the ULA will only be providing pixel data for 40µs in each
75 scanline.
76
77 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
78 each scanline can be divided into 1024 cycles, although only 640 at most are
79 actively used to provide pixel data. Pixel data production should only occur
80 within a certain period on each scanline, approximately 262 cycles after the
81 start of hsync:
82
83 active video period = 51.95µs
84 pixel data period = 40µs
85 total silent period = 51.95µs - 40µs = 11.95µs
86 silent periods (before and after) = 11.95µs / 2 = 5.975µs
87 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
88 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
89 pixel data period start cycle = 16.375µs / 62.5ns = 262
90
91 By choosing a number divisible by 8, the RAM access mechanism can be
92 synchronised with the pixel production. Thus, 264 is a more appropriate start
93 cycle.
94
95 The "vertical blanking period", meaning the period before picture information
96 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
97 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
98 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
99 occurs half way through the 23rd scanline period measured from the start of
100 vsync:
101
102 10 20 23
103 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
104 Line from 1: 0 22 3
105 Line on screen: .:::::VVVVV::::: 12233445566
106 |_________________________________________________|
107 25 line vertical blanking period
108
109 In the second field of a frame, the first visible scanline coincides with the
110 24th scanline period measured from the start of line 313 in the frame:
111
112 310 336
113 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
114 Line from 313: 0 23
115 Line on screen: 88:::::VVVVV:::: 11223344
116 288 | |
117 |_________________________________________________|
118 25 line vertical blanking period
119
120 In order to consider only full lines, we might consider the start of each
121 frame to occur 23 lines after the start of vsync.
122
123 Again, it is likely that pixel data production should only occur on scanlines
124 within a certain period on each frame. The "625/50" document indicates that
125 only a certain region is "safe" to use, suggesting a vertically centred region
126 with approximately 15 blank lines above and below the picture. Thus, the start
127 of the picture could be chosen as 38 lines after the start of vsync.
128
129 See: Acorn Electron Advanced User Guide
130 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
131 See: http://en.wikipedia.org/wiki/PAL
132 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
133 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
134 http://lipas.uwasa.fi/~f76998/video/modes/
135 See: PAL TV timing and voltages
136 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
137 See: Line Standards
138 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
139 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
140 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
141 See: Acorn Electron Service Manual
142 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
143
144 Interrupts
145 ----------
146
147 The ULA generates IRQs (maskable interrupts) according to certain conditions
148 and these conditions are controlled by location &FE00:
149
150 * Vertical sync (bottom of displayed screen)
151 * 50MHz real time clock
152 * Transmit data empty
153 * Receive data full
154 * High tone detect
155
156 The ULA is also used to clear interrupt conditions through location &FE05. Of
157 particular significance is bit 7, which must be set if an NMI (non-maskable
158 interrupt) has occurred and has thus suspended ULA access to memory, restoring
159 the normal function of the ULA.
160
161 ROM Paging
162 ----------
163
164 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
165 mappings exist:
166
167 8 keyboard
168 9 keyboard (duplicate)
169 10 BASIC ROM
170 11 BASIC ROM (duplicate)
171
172 Paging in a ROM involves the following procedure:
173
174 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
175 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
176 selected.
177 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
178 whilst writing the desired ROM number n in bits 0 to 2.
179
180 Shadow/Expanded Memory
181 ----------------------
182
183 The Electron exposes all sixteen address lines and all eight data lines
184 through the expansion bus. Using such lines, it is possible to provide
185 additional memory - typically sideways ROM and RAM - on expansion cards and
186 through cartridges, although the official cartridge specification provides
187 fewer address lines and only seeks to provide access to memory in 16K units.
188
189 Various modifications and upgrades were developed to offer "turbo"
190 capabilities to the Electron, permitting the CPU to access a separate 8K of
191 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
192 the ULA through additional logic. However, an enhanced ULA might support
193 independent CPU access to memory over the expansion bus by allowing itself to
194 be discharged from providing access to memory, potentially for a range of
195 addresses, and for the CPU to communicate with external memory uninterrupted.
196
197 Hardware Scrolling
198 ------------------
199
200 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
201 the least significant 5 bits being zero, thus limiting the scrolling
202 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
203 using the same layout of these addresses.
204
205 |--&FE02--------------| |--&FE03--------------|
206 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
207
208 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
209
210 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
211 memory to pixel locations is character oriented. A change in 8 bytes would
212 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
213 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
214 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
215 Guide).
216
217 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
218 of changing the screen address by 2 bytes is the change in the number of lines
219 from the initial and final character rows that need reading by the ULA, which
220 would need to maintain this state information (although this is a relatively
221 trivial change). Another pitfall is the complication that might be introduced
222 to software writing bitmaps of character height to the screen.
223
224 Region Blanking
225 ---------------
226
227 The problem of permitting character-oriented blitting in programs whilst
228 scrolling the screen by sub-character amounts could be mitigated by permitting
229 a region of the display to be blank, such as the final lines of the display.
230 Consider the following vertical scrolling by 2 bytes that would cause an
231 initial character row of 6 lines and a final character row of 2 lines:
232
233 6 lines - initial, partial character row
234 248 lines - 31 complete rows
235 2 lines - final, partial character row
236
237 If a routine were in use that wrote 8 line bitmaps to the partial character
238 row now split in two, it would be advisable to hide one of the regions in
239 order to prevent content appearing in the wrong place on screen (such as
240 content meant to appear at the top "leaking" onto the bottom). Blanking 6
241 lines would be sufficient, as can be seen from the following cases.
242
243 Scrolling up by 2 lines:
244
245 6 lines - initial, partial character row
246 240 lines - 30 complete rows
247 4 lines - part of 1 complete row
248 -----------------------------------------------------------------
249 4 lines - part of 1 complete row (hidden to maintain 250 lines)
250 2 lines - final, partial character row (hidden)
251
252 Scrolling down by 2 lines:
253
254 2 lines - initial, partial character row
255 248 lines - 31 complete rows
256 ----------------------------------------------------------
257 6 lines - final, partial character row (hidden)
258
259 Thus, in this case, region blanking would impose a 250 line display with the
260 bottom 6 lines blank.
261
262 Screen Height Adjustment
263 ------------------------
264
265 The height of the screen could be configurable in order to reduce screen
266 memory consumption. This is not quite done in MODE 3 and 6 since the start of
267 the screen appears to be rounded down to the nearest page, but by reducing the
268 height by amounts more than a page, savings would be possible. For example:
269
270 Screen width Depth Height Bytes per line Saving in bytes Start address
271 ------------ ----- ------ -------------- --------------- -------------
272 640 1 252 80 320 &3140 -> &3100
273 640 1 248 80 640 &3280 -> &3200
274 320 1 240 40 640 &5A80 -> &5A00
275 320 2 240 80 1280 &3500
276
277 Palette Definition
278 ------------------
279
280 Since all memory accesses go via the ULA, an enhanced ULA could employ more
281 specific addresses than &FE*X to perform enhanced functions. For example, the
282 palette control is done using &FE*8-F and merely involves selecting predefined
283 colours, whereas an enhanced ULA could support the redefinition of all 16
284 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
285 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
286 specifications similar to those used on the Archimedes.
287
288 The principal limitation here is actually the hardware: the Electron has only
289 a single output line for each of the red, green and blue channels, and if
290 those outputs are strictly digital and can only be set to a "high" and "low"
291 value, then only the existing eight colours are possible. If a modern ULA were
292 able to output analogue values, it would still need to be assessed whether the
293 circuitry could successfully handle and propagate such values. Various sources
294 indicate that only "TTL levels" are supported by the RGB output circuit, and
295 since there are 74LS08 AND logic gates involved in the RGB component outputs
296 from the ULA, it is likely that the ULA is expected to provide only "high" or
297 "low" values.
298
299 Palette Definition Lists
300 ------------------------
301
302 It can be useful to redefine the palette in order to change the colours
303 available for a particular region of the screen, particularly in modes where
304 the choice of colours is constrained, and if an increased colour depth were
305 available, palette redefinition would be useful to give the illusion of more
306 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
307 by using interrupt-driven timers, but a more efficient approach would involve
308 presenting lists of palette definitions to the ULA so that it can change the
309 palette at a particular display line.
310
311 One might define a palette redefinition list in a region of memory and then
312 communicate its contents to the ULA by writing the address and length of the
313 list, along with the display line at which the palette is to be changed, to
314 ULA registers such that the ULA buffers the list and performs the redefinition
315 at the appropriate time. Throughput/bandwidth considerations might impose
316 restrictions on the practical length of such a list, however.
317
318 Palette-Free Modes
319 ------------------
320
321 Palette-free modes might be defined where bit values directly correspond to
322 the red, green and blue channels, although this would mostly make sense only
323 for modes with depths greater than the standard 4 bits per pixel, and such
324 modes would require more memory than MODE 2 if they were to have an acceptable
325 resolution.
326
327 Display Suspend
328 ---------------
329
330 Especially when writing to the screen memory, it could be beneficial to be
331 able to suspend the ULA's access to the memory, instead producing blank values
332 for all screen pixels until a program is ready to reveal the screen. This is
333 different from palette blanking since with a blank palette, the ULA is still
334 reading screen memory and translating its contents into pixel values that end
335 up being blank.
336
337 This function is reminiscent of a capability of the ZX81, albeit necessary on
338 that hardware to reduce the load on the system CPU which was responsible for
339 producing the video output.
340
341 Hardware Sprites
342 ----------------
343
344 An enhanced ULA might provide hardware sprites, but this would be done in an
345 way that is incompatible with the standard ULA, since no &FE*X locations are
346 available for allocation. To keep the facility simple, hardware sprites would
347 have a standard byte width and height.
348
349 The specification of sprites could involve the reservation of 16 locations
350 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
351 location pair referring to the sprite data. By limiting the ULA to dealing
352 with a fixed number of sprites, the work required inside the ULA would be
353 reduced since it would avoid having to deal with arbitrary numbers of sprites.
354
355 The principal limitation on providing hardware sprites is that of having to
356 obtain sprite data, given that the ULA is usually required to retrieve screen
357 data, and given the lack of memory bandwidth available to retrieve sprite data
358 (particularly from multiple sprites supposedly at the same position) and
359 screen data simultaneously. Although the ULA could potentially read sprite
360 data and screen data in alternate memory accesses in screen modes where the
361 bandwidth is not already fully utilised, this would result in a degradation of
362 performance.
363
364 Additional Screen Mode Configurations
365 -------------------------------------
366
367 Alternative screen mode configurations could be supported. The ULA has to
368 produce 640 pixel values across the screen, with pixel doubling or quadrupling
369 employed to fill the screen width:
370
371 Screen width Columns Scaling Depth Bytes
372 ------------ ------- ------- ----- -----
373 640 80 x1 1 80
374 320 40 x2 1, 2 40, 80
375 160 20 x4 2, 4 40, 80
376
377 It must also use at most 80 byte-sized memory accesses to provide the
378 information for the display. Given that characters must occupy an 8x8 pixel
379 array, if a configuration featuring anything other than 20, 40 or 80 character
380 columns is to be supported, compromises must be made such as the introduction
381 of blank pixels either between characters (such as occurs between rows in MODE
382 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
383 in MODE 3 and 6). Consider the following configuration:
384
385 Screen width Columns Scaling Depth Bytes Blank
386 ------------ ------- ------- ----- ------ -----
387 208 26 x3 1, 2 26, 52 16
388
389 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
390 colours could be provided, with 16 blank pixel values (out of a total of 640)
391 generated either at the start or end (or split between the start and end) of
392 each scanline.
393
394 Character Attributes
395 --------------------
396
397 The BBC Micro MODE 7 employs something resembling character attributes to
398 support teletext displays, but depends on circuitry providing a character
399 generator. The ZX Spectrum, on the other hand, provides character attributes
400 as a means of colouring bitmapped graphics. Although such a feature is very
401 limiting as the sole means of providing multicolour graphics, in situations
402 where the choice is between low resolution multicolour graphics or high
403 resolution monochrome graphics, character attributes provide a potentially
404 useful compromise.
405
406 For each byte read, the ULA must deliver 8 pixel values (out of a total of
407 640) to the video output, doing so by either emptying its pixel buffer on a
408 pixel per cycle basis, or by multiplying pixels and thus holding them for more
409 than one cycle. For example for a screen mode having 640 pixels in width:
410
411 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
412 Reads: B B
413 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
414
415 And for a screen mode having 320 pixels in width:
416
417 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
418 Reads: B
419 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
420
421 However, in modes where less than 80 bytes are required to generate the pixel
422 values, an enhanced ULA might be able to read additional bytes between those
423 providing the bitmapped graphics data:
424
425 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
426 Reads: B A
427 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
428
429 These additional bytes could provide colour information for the bitmapped data
430 in the following character column (of 8 pixels). Since it would be desirable
431 to apply attribute data to the first column, the initial 8 cycles might be
432 configured to not produce pixel values.
433
434 For an entire character, attribute data need only be read for the first row of
435 pixels for a character. The subsequent rows would have attribute information
436 applied to them, although this would require the attribute data to be stored
437 in some kind of buffer. Thus, the following access pattern would be observed:
438
439 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
440
441 A whole byte used for colour information for a whole character would result in
442 a choice of 256 colours, and this might be somewhat excessive. By only reading
443 attribute bytes at every other opportunity, a choice of 16 colours could be
444 applied individually to two characters.
445
446 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
447 Reads: B A B -
448 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
449
450 Further reductions in attribute data access, offering 4 colours for every
451 character in a four character block, for example, might also be worth
452 considering.
453
454 Consider the following configurations for screen modes with a colour depth of
455 1 bit per pixel for bitmap information:
456
457 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
458 ------------ ------- ------- --------- --------- ------- ------------
459 320 40 x2 40 40 256 &5300
460 320 40 x2 40 20 16 &5580 -> &5500
461 320 40 x2 40 10 4 &56C0 -> &5600
462 208 26 x3 26 26 256 &62C0 -> &6200
463 208 26 x3 26 13 16 &6460 -> &6400
464
465 MODE 7 Emulation using Character Attributes
466 -------------------------------------------
467
468 If the scheme of applying attributes to character regions were employed to
469 emulate MODE 7, in conjunction with the MODE 6 display technique, the
470 following configuration would be required:
471
472 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
473 ------------ ------- ---- --------- --------- ------- ------------
474 320 40 25 40 20 16 &5ECC -> &5E00
475 320 40 25 40 10 4 &5FC6 -> &5F00
476
477 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
478 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
479 at least make a limited 40-column multicolour mode available as a substitute
480 for MODE 7.
481
482 Enhanced Graphics and Mode Layouts
483 ----------------------------------
484
485 Screen modes with different screen memory mappings, higher resolutions and
486 larger colour depths might be possible, but this would in most cases involve
487 the allocation of more screen memory, and the ULA would probably then be
488 obliged to page in such memory for the CPU to be able to sensibly access it
489 all. Merely changing the memory mappings in order to have Archimedes-style
490 row-oriented screen addresses (instead of character-oriented addresses) could
491 be done for the existing modes, but this might not be sufficiently beneficial,
492 especially since accessing regions of the screen would involve incrementing
493 pointers by amounts that are inconvenient on an 8-bit CPU.
494
495 Genlock Support
496 ---------------
497
498 The ULA generates a video signal in conjunction with circuitry producing the
499 output features necessary for the correct display of the screen image.
500 However, it appears that the ULA drives the video synchronisation mechanism
501 instead of reacting to an existing signal. Genlock support might be possible
502 if the ULA were made to be responsive to such external signals, resetting its
503 address generators upon receiving synchronisation events.
504
505 Enhanced Sound
506 --------------
507
508 The standard ULA reserves &FE*6 for sound generation and cassette
509 input/output, thus making it impossible to support multiple channels within
510 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
511 and an enhanced ULA could adopt this interface.
512
513 The BBC Micro uses the SN76489 chip to produce sound, and the entire
514 functionality of this chip could be emulated for enhanced sound, with a subset
515 of the functionality exposed via the &FE*6 interface.
516
517 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
518
519 Waveform Upload
520 ---------------
521
522 As with a hardware sprite function, waveforms could be uploaded or referenced
523 using locations as registers referencing memory regions.
524
525 Sound Input/Output
526 ------------------
527
528 Since the ULA already controls audio input/output for cassette-based data, it
529 would have been interesting to entertain the idea of sampling and output of
530 sounds through the cassette interface. However, a significant amount of
531 circuitry is employed to process the input signal for use by the ULA and to
532 process the output signal for recording.
533
534 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
535
536 BBC ULA Compatibility
537 ---------------------
538
539 Although some new ULA functions could be defined in a way that is also
540 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
541 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
542 map, but controls various functions specific to the 6845 video controller;
543 &FE08-F is reserved for the serial controller. It therefore becomes possible
544 to disregard compatibility where compatibility is already disregarded for a
545 particular area of functionality.
546
547 &FE20-F maps to video ULA functionality on the BBC Micro which provides
548 control over the palette (using address &FE21, compared to &FE07-F on the
549 Electron) and other system-specific functions. Since the location usage is
550 generally incompatible, this region could be reused for other purposes.
551
552 ULA Pin Functions
553 -----------------
554
555 The functions of the ULA pins are described in the Electron Service Manual. Of
556 interest to video processing are the following:
557
558 CSYNC (low during horizontal or vertical synchronisation periods, high
559 otherwise)
560
561 HS (low during horizontal synchronisation periods, high otherwise)
562
563 RED, GREEN, BLUE (pixel colour outputs)
564
565 CLOCK IN (a 16MHz clock input, 4V peak to peak)
566
567 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
568
569 More general memory access pins:
570
571 RAM0...RAM3 (data lines to/from the RAM)
572
573 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
574
575 RAS (row address strobe setting the row address on a negative edge - see the
576 timing notes)
577
578 CAS (column address strobe setting the column address on a negative edge -
579 see the timing notes)
580
581 WE (sets write enable with logic 0, read with logic 1)
582
583 ROM (select data access from ROM)
584
585 CPU-oriented memory access pins:
586
587 A0...A15 (CPU address lines)
588
589 PD0...PD7 (CPU data lines)
590
591 R/W (indicates CPU write with logic 0, CPU read with logic 1)
592
593 Interrupt-related pins:
594
595 NMI (CPU request for uninterrupted 1MHz access to memory)
596
597 IRQ (signal event to CPU)
598
599 POR (power-on reset, resetting the ULA on a positive edge and asserting the
600 CPU's RST pin)
601
602 RST (master reset for the CPU signalled on power-up and by the Break key)
603
604 Keyboard-related pins:
605
606 KBD0...KBD3 (keyboard inputs)
607
608 CAPS LOCK (control status LED)
609
610 Sound-related pins:
611
612 SOUND O/P (sound output using internal oscillator)
613
614 Cassette-related pins:
615
616 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
617
618 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
619
620 CAS RC (detect high tone)
621
622 CAS MO (motor relay output)
623
624 ÷13 IN (~1200 baud clock input)
625
626 References
627 ----------
628
629 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm