1 #!/usr/bin/env python 2 3 """ 4 Acorn Electron ULA simulation. 5 6 Copyright (C) 2011, 2012, 2013, 2014, 2016 Paul Boddie <paul@boddie.org.uk> 7 8 This program is free software; you can redistribute it and/or modify it under 9 the terms of the GNU General Public License as published by the Free Software 10 Foundation; either version 3 of the License, or (at your option) any later 11 version. 12 13 This program is distributed in the hope that it will be useful, but WITHOUT ANY 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A 15 PARTICULAR PURPOSE. See the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License along 18 with this program. If not, see <http://www.gnu.org/licenses/>. 19 """ 20 21 from array import array 22 from itertools import repeat 23 24 LINES_PER_ROW = 8 # the number of pixel lines per character row 25 MAX_HEIGHT = 256 # the height of the screen in pixels 26 MAX_WIDTH = 640 # the width of the screen in pixels 27 28 MAX_CSYNC = 2 # the scanline during which vsync ends 29 MIN_PIXELLINE = 28 # the first scanline involving pixel generation 30 MAX_SCANLINE = 312 # the number of scanlines in each frame 31 32 MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT 33 34 MAX_HSYNC = 64 # the number of cycles in each hsync period 35 MIN_PIXELPOS = 256 # the first cycle involving pixel generation 36 MAX_SCANPOS = 1024 # the number of cycles in each scanline 37 38 MAX_PIXELPOS = MIN_PIXELPOS + MAX_WIDTH 39 40 PIXEL_POSITIONS = 8 # the number of pixel positions per byte 41 # (doubled or quadrupled in lower resolutions) 42 43 SCREEN_LIMIT = 0x8000 # the first address after the screen memory 44 MAX_MEMORY = 0x10000 # the number of addressable memory locations 45 MAX_RAM = 0x10000 # the number of addressable RAM locations (64Kb in each IC) 46 BLANK = (0, 0, 0) 47 48 def update(ula): 49 50 """ 51 Update the 'ula' for one frame. Return the resulting screen. 52 """ 53 54 video = ula.video 55 56 i = 0 57 limit = MAX_SCANLINE * MAX_SCANPOS 58 while i < limit: 59 ula.update() 60 video.update() 61 i += 1 62 63 return video.screen 64 65 class Video: 66 67 """ 68 A class representing the video circuitry. 69 """ 70 71 def __init__(self): 72 self.screen = array("B", repeat(0, MAX_WIDTH * 3 * MAX_HEIGHT)) 73 self.colour = BLANK 74 self.csync = 1 75 self.hs = 1 76 self.x = 0 77 self.y = 0 78 79 def set_csync(self, value): 80 if self.csync and not value: 81 self.y = 0 82 self.pos = 0 83 self.csync = value 84 85 def set_hs(self, value): 86 if self.hs and not value: 87 self.x = 0 88 self.y += 1 89 self.hs = value 90 91 def update(self): 92 if MIN_PIXELLINE <= self.y < MAX_PIXELLINE: 93 if MIN_PIXELPOS + 8 <= self.x < MAX_PIXELPOS + 8: 94 self.screen[self.pos] = self.colour[0]; self.pos += 1 95 self.screen[self.pos] = self.colour[1]; self.pos += 1 96 self.screen[self.pos] = self.colour[2]; self.pos += 1 97 self.x += 1 98 99 class RAM: 100 101 """ 102 A class representing the RAM circuits (IC4 to IC7). Each circuit 103 traditionally holds 64 kilobits, with each access obtaining 1 bit from each 104 IC, and thus two accesses being required to obtain a whole byte. Here, we 105 model the circuits with a list of 65536 half-bytes with each bit in a 106 half-byte representing a bit stored on a separate IC. 107 """ 108 109 def __init__(self): 110 111 "Initialise the RAM circuits." 112 113 self.memory = [0] * MAX_RAM 114 self.row_address = 0 115 self.column_address = 0 116 self.data = 0 117 118 def row_select(self, address): 119 120 "The operation of asserting a row 'address' via RA0...RA7." 121 122 self.row_address = address 123 124 def row_deselect(self): 125 pass 126 127 def column_select(self, address): 128 129 "The operation of asserting a column 'address' via RA0...RA7." 130 131 self.column_address = address 132 133 # Read the data. 134 135 self.data = self.memory[self.row_address << 8 | self.column_address] 136 137 def column_deselect(self): 138 pass 139 140 # Convenience methods. 141 142 def fill(self, start, end, value): 143 for i in xrange(start, end): 144 self.memory[i << 1] = value >> 4 145 self.memory[i << 1 | 0x1] = value & 0xf 146 147 class ShiftRegister: 148 149 """ 150 A class representing a shift register, used for the internal state of the 151 ULA within each 2MHz period. 152 """ 153 154 def __init__(self): 155 self.state = [0] * 8 156 self.input = 0 157 158 def set_input(self, input): 159 self.input = input 160 161 def shift(self): 162 163 # NOTE: This is not meant to be "nice" Python, but instead models the 164 # NOTE: propagation of state through the latches. 165 166 self.state[0], self.state[1], self.state[2], self.state[3], \ 167 self.state[4], self.state[5], self.state[6], self.state[7] = \ 168 self.input, self.state[0], self.state[1], self.state[2], \ 169 self.state[3], self.state[4], self.state[5], self.state[6] 170 171 def __getitem__(self, i): 172 return self.state[i] 173 174 class ULA: 175 176 """ 177 A class providing the ULA functionality. Instances of this class refer to 178 the system memory, maintain internal state (such as information about the 179 current screen mode), and provide outputs (such as the current pixel 180 colour). 181 """ 182 183 modes = [ 184 (640, 1, 32), (320, 2, 32), (160, 4, 32), # (width, depth, rows) 185 (640, 1, 25), (320, 1, 32), (160, 2, 32), 186 (320, 1, 25) 187 ] 188 189 palette = range(0, 8) * 2 190 191 def __init__(self, ram, video): 192 193 "Initialise the ULA with the given 'ram' and 'video' instances." 194 195 self.ram = ram 196 self.video = video 197 self.set_mode(6) 198 199 self.reset() 200 201 def reset(self): 202 203 "Reset the ULA." 204 205 # General state. 206 207 self.nmi = 0 # no NMI asserted initially 208 self.irq_vsync = 0 # no IRQ asserted initially 209 210 # Communication. 211 212 self.ram_address = 0 # address given to the RAM via RA0...RA7 213 self.data = 0 # data read from the RAM via RAM0...RAM3 214 self.cpu_address = 0 # address selected by the CPU via A0...A15 215 self.cpu_read = 0 # data read/write by the CPU selected using R/W 216 217 # Internal state. 218 219 self.access = 0 # counter used to determine whether a byte needs reading 220 self.have_pixels = 0 # whether pixel data has been read 221 self.writing_pixels = 0 # whether pixel data can be written 222 self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data 223 224 self.cycle = ShiftRegister() # 8-state counter within each 2MHz period 225 226 self.cycle.set_input(1) # assert the input to set the first state output 227 self.cycle.shift() 228 self.cycle.set_input(0) # reset the input since only one state output will be active 229 230 self.reset_vertical() 231 232 def set_mode(self, mode): 233 234 """ 235 For the given 'mode', initialise the... 236 237 * width in pixels 238 * colour depth in bits per pixel 239 * number of character rows 240 * character row size in bytes 241 * screen size in bytes 242 * default screen start address 243 * horizontal pixel scaling factor 244 * line spacing in pixels 245 * number of entries in the pixel buffer 246 247 The ULA should be reset after a mode switch in order to cleanly display 248 a full screen. 249 """ 250 251 self.width, self.depth, rows = self.modes[mode] 252 253 columns = (self.width * self.depth) / 8 # bits read -> bytes read 254 self.access_frequency = 80 / columns # cycle frequency for reading bytes 255 row_size = columns * LINES_PER_ROW 256 257 # Memory access configuration. 258 # Note the limitation on positioning the screen start. 259 260 screen_size = row_size * rows 261 self.screen_start = (SCREEN_LIMIT - screen_size) & 0xff00 262 self.screen_size = SCREEN_LIMIT - self.screen_start 263 264 # Scanline configuration. 265 266 self.xscale = MAX_WIDTH / self.width # pixel width in display pixels 267 self.spacing = MAX_HEIGHT / rows - LINES_PER_ROW # pixels between rows 268 269 # Start of unused region. 270 271 self.footer = rows * LINES_PER_ROW 272 self.margin = MAX_SCANLINE - rows * (LINES_PER_ROW + self.spacing) + self.spacing 273 274 def vsync(self, value=0): 275 276 "Signal the start of a frame." 277 278 self.csync = value 279 self.video.set_csync(value) 280 281 def hsync(self, value=0): 282 283 "Signal the end of a scanline." 284 285 self.hs = value 286 self.video.set_hs(value) 287 288 def reset_vertical(self): 289 290 "Signal the start of a frame." 291 292 self.line_start = self.address = self.screen_start 293 self.line = self.line_start % LINES_PER_ROW 294 self.ssub = 0 295 self.y = 0 296 self.x = 0 297 298 def reset_horizontal(self): 299 300 "Reset horizontal state within the active region of the frame." 301 302 self.y += 1 303 self.x = 0 304 305 if not self.inside_frame(): 306 return 307 308 # Support spacing between character rows. 309 310 if self.ssub: 311 self.ssub -= 1 312 return 313 314 self.line += 1 315 316 # If not on a row boundary, move to the next line. 317 318 if self.line % LINES_PER_ROW: 319 self.address = self.line_start + 1 320 self.wrap_address() 321 322 # After the end of the last line in a row, the address should already 323 # have been positioned on the last line of the next column. 324 325 else: 326 self.address -= LINES_PER_ROW - 1 327 self.wrap_address() 328 329 # Test for the footer region. 330 331 if self.spacing and self.line == self.footer: 332 self.ssub = self.margin 333 return 334 335 # Support spacing between character rows. 336 337 self.ssub = self.spacing 338 339 self.line_start = self.address 340 341 def in_frame(self): return MIN_PIXELLINE <= self.y < MAX_PIXELLINE 342 def inside_frame(self): return MIN_PIXELLINE < self.y < MAX_PIXELLINE 343 def read_pixels(self): return MIN_PIXELPOS <= self.x < MAX_PIXELPOS and self.in_frame() 344 345 def update(self): 346 347 """ 348 Update the state of the ULA for each clock cycle. This involves updating 349 the pixel colour by reading from the pixel buffer. 350 """ 351 352 # Detect the end of the scanline. 353 354 if self.x == MAX_SCANPOS: 355 self.reset_horizontal() 356 357 # Detect the end of the frame. 358 359 if self.y == MAX_SCANLINE: 360 self.reset_vertical() 361 362 363 364 # Clock management. 365 366 would_access_ram = self.access == 0 and self.read_pixels() and not self.ssub 367 access_ram = not self.nmi and would_access_ram 368 369 # Set row address (for ULA access only). 370 371 if self.cycle[0]: 372 373 # Either assert a required address or propagate the CPU address. 374 375 if access_ram: 376 self.init_row_address(self.address) 377 else: 378 self.init_row_address(self.cpu_address) 379 380 # Initialise the pixel buffer if appropriate. 381 382 if not self.writing_pixels and self.have_pixels: 383 self.buffer_index = 0 384 self.fill_pixel_buffer() 385 self.writing_pixels = 1 386 387 # Latch row address, set column address (for ULA access only). 388 389 elif self.cycle[1]: 390 391 # Select an address needed by the ULA or CPU. 392 393 self.ram.row_select(self.ram_address) 394 395 # Either assert a required address or propagate the CPU address. 396 397 if access_ram: 398 self.init_column_address(self.address, 0) 399 else: 400 self.init_column_address(self.cpu_address, 0) 401 402 # Latch column address. 403 404 elif self.cycle[2]: 405 406 # Select an address needed by the ULA or CPU. 407 408 self.ram.column_select(self.ram_address) 409 410 # Read 4 bits (for ULA access only). 411 # NOTE: Perhaps map alternate bits, not half-bytes. 412 413 elif self.cycle[3]: 414 415 # Either read from a required address or transfer CPU data. 416 417 if access_ram: 418 self.data = self.ram.data << 4 419 else: 420 self.cpu_transfer_high() 421 422 # Set column address (for ULA access only). 423 424 elif self.cycle[4]: 425 self.ram.column_deselect() 426 427 # Either assert a required address or propagate the CPU address. 428 429 if access_ram: 430 self.init_column_address(self.address, 1) 431 else: 432 self.init_column_address(self.cpu_address, 1) 433 434 # Latch column address. 435 436 elif self.cycle[5]: 437 438 # Select an address needed by the ULA or CPU. 439 440 self.ram.column_select(self.ram_address) 441 442 # Read 4 bits (for ULA access only). 443 # NOTE: Perhaps map alternate bits, not half-bytes. 444 445 elif self.cycle[6]: 446 447 # Either read from a required address or transfer CPU data. 448 449 if access_ram: 450 self.data = self.data | self.ram.data 451 self.have_pixels = 1 452 else: 453 self.cpu_transfer_low() 454 455 # Advance to the next column even if an NMI is asserted. 456 457 if would_access_ram: 458 self.address += LINES_PER_ROW 459 self.wrap_address() 460 461 # Reset addresses. 462 463 elif self.cycle[7]: 464 self.ram.column_deselect() 465 self.ram.row_deselect() 466 467 # Update the RAM access controller. 468 469 self.access = (self.access + 1) % self.access_frequency 470 471 # Update the state of the device. 472 473 self.cycle.set_input(self.cycle[7]) 474 self.cycle.shift() 475 476 477 478 # Video signalling. 479 480 # Detect any sync conditions. 481 482 if self.x == 0: 483 self.hsync() 484 if self.y == 0: 485 self.vsync() 486 self.irq_vsync = 0 487 elif self.y == MAX_PIXELLINE: 488 self.irq_vsync = 1 489 490 # Detect the end of hsync. 491 492 elif self.x == MAX_HSYNC: 493 self.hsync(1) 494 495 # Detect the end of vsync. 496 497 elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2: 498 self.vsync(1) 499 500 501 self.x += 1 502 503 504 # Pixel production. 505 506 # Detect spacing between character rows. 507 508 if not self.writing_pixels or self.ssub: 509 self.video.colour = BLANK 510 511 # For pixels within the frame, obtain and output the value. 512 513 else: 514 self.video.colour = self.buffer[self.buffer_index] 515 516 # Scale pixels horizontally, only accessing the next pixel value 517 # after the required number of scan positions. 518 519 if self.x % self.xscale == 0: 520 self.buffer_index += 1 521 522 # Finish writing pixels. 523 524 if self.x % PIXEL_POSITIONS == 0: 525 self.writing_pixels = 0 526 527 def fill_pixel_buffer(self): 528 529 """ 530 Fill the pixel buffer by translating memory content for the current 531 mode. 532 """ 533 534 byte_value = self.data # which should have been read automatically 535 536 i = 0 537 for colour in decode(byte_value, self.depth): 538 self.buffer[i] = get_physical_colour(self.palette[colour]) 539 i += 1 540 541 def wrap_address(self): 542 if self.address >= SCREEN_LIMIT: 543 self.address -= self.screen_size 544 545 def init_row_address(self, address): 546 self.ram_address = (address & 0xff80) >> 7 547 548 def init_column_address(self, address, offset): 549 self.ram_address = (address & 0x7f) << 1 | offset 550 551 def cpu_transfer_high(self): 552 if self.cpu_read: 553 self.cpu_data = self.ram.data << 4 554 555 def cpu_transfer_low(self): 556 if self.cpu_read: 557 self.cpu_data = self.data | self.ram.data 558 559 def get_physical_colour(value): 560 561 """ 562 Return the physical colour as an RGB triple for the given 'value'. 563 """ 564 565 return value & 1, value >> 1 & 1, value >> 2 & 1 566 567 def decode(value, depth): 568 569 """ 570 Decode the given byte 'value' according to the 'depth' in bits per pixel, 571 returning a sequence of pixel values. 572 """ 573 574 if depth == 1: 575 return (value >> 7, value >> 6 & 1, value >> 5 & 1, value >> 4 & 1, 576 value >> 3 & 1, value >> 2 & 1, value >> 1 & 1, value & 1) 577 elif depth == 2: 578 return (value >> 6 & 2 | value >> 3 & 1, value >> 5 & 2 | value >> 2 & 1, 579 value >> 4 & 2 | value >> 1 & 1, value >> 3 & 2 | value & 1) 580 elif depth == 4: 581 return (value >> 4 & 8 | value >> 3 & 4 | value >> 2 & 2 | value >> 1 & 1, 582 value >> 3 & 8 | value >> 2 & 4 | value >> 1 & 2 | value & 1) 583 else: 584 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 585 586 # Convenience functions. 587 588 def encode(values, depth): 589 590 """ 591 Encode the given 'values' according to the 'depth' in bits per pixel, 592 returning a byte value for the pixels. 593 """ 594 595 result = 0 596 597 if depth == 1: 598 for value in values: 599 result = result << 1 | (value & 1) 600 elif depth == 2: 601 for value in values: 602 result = result << 1 | (value & 2) << 3 | (value & 1) 603 elif depth == 4: 604 for value in values: 605 result = result << 1 | (value & 8) << 3 | (value & 4) << 2 | (value & 2) << 1 | (value & 1) 606 else: 607 raise ValueError, "Only depths of 1, 2 and 4 are supported, not %d." % depth 608 609 return result 610 611 def get_ula(): 612 613 "Return a ULA initialised with a memory array and video." 614 615 return ULA(get_ram(), get_video()) 616 617 def get_video(): 618 619 "Return a video circuit." 620 621 return Video() 622 623 def get_ram(): 624 625 "Return an instance representing the computer's RAM hardware." 626 627 return RAM() 628 629 # Test program providing coverage (necessary for compilers like Shedskin). 630 631 if __name__ == "__main__": 632 ula = get_ula() 633 ula.set_mode(2) 634 ula.reset() 635 ula.ram.fill(0x5800 - 320, 0x8000, encode((2, 7), 4)) 636 637 # Make a simple two-dimensional array of tuples (three-dimensional in pygame 638 # terminology). 639 640 a = update(ula) 641 642 # vim: tabstop=4 expandtab shiftwidth=4