1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 (In fact, since the ULA is seeking to provide an image for an interlaced
36 625-line display, there are in fact two "fields" involved, one providing 312
37 scanlines and one providing 313 scanlines. See below for a description of the
38 video system.)
39
40 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
41 each providing two bits of each byte) using two cycles within the 500ns period
42 of the 2MHz clock to complete each access operation. Since the CPU and ULA
43 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
44 effectively run at 1MHz (since every other 500ns period involves the ULA
45 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
46 frequency is divided by the ULA (IC1) depending on the screen mode in use.
47
48 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
49 patterns corresponding to 16MHz cycles are required:
50
51 Time (ns): 0-------------- 500------------- ...
52 2 MHz cycle: 0 1 ...
53 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
54 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
55 ~RAS: /---\___________/---\___________ ...
56 ~CAS: /-----\___/-\___/-----\___/-\___ ...
57 Address events: A B C A B C ...
58 Data events: F S F S ...
59
60 ~RAS ops: 1 0 1 0 ...
61 ~CAS ops: 1 0 1 0 1 0 1 0 ...
62
63 Address ops: a b c a b c ...
64 Data ops: s f s f ...
65
66 ~WE: ......W ...
67 PHI OUT: \_______________/--------------- ...
68 CPU (RAM): L D ...
69 RnW: R ...
70
71 PHI OUT: \_______/-------\_______/------- ...
72 CPU (ROM): L D L D ...
73 RnW: R R ...
74
75 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
76 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
77 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
78
79 Here, "A" and "B" respectively indicate the row and first column addresses
80 being latched into the RAM (on a negative edge for ~RAS and ~CAS
81 respectively), and "C" indicates the second column address being latched into
82 the RAM. Presumably, the first and second half-bytes can be read at "F" and
83 "S" respectively, and the row and column addresses must be made available at
84 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
85 "s" for the first and second half-bytes respectively.
86
87 For the CPU, "L" indicates the point at which an address is taken from the CPU
88 address bus, on a negative edge of PHI OUT, with "D" being the point at which
89 data may either be read or be asserted for writing, on a positive edge of PHI
90 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
91 for writing or high for reading, and thus propagates RnW from the CPU, this
92 would need to be done before data would be retrieved and, according to the
93 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
94 brought low.
95
96 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
97 address access time of 90ns (maximum), which appears to mean that ~RAS must be
98 held low for at least 150ns and that ~CAS must be held low for at least 90ns
99 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
100 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
101 is 1.5 cycles.
102
103 Note that the Service Manual refers to the negative edge of RAS and CAS, but
104 the datasheet for the similar TM4164EC4 product shows latching on the negative
105 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
106 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
107 "page mode" provides the appropriate behaviour for that particular product.
108
109 The CPU, when accessing the RAM alone, apparently does not make use of the
110 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
111 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
112 accessing ROM (and potentially sideways RAM). The principal limitation is the
113 amount of time needed between issuing an address and receiving an entire byte
114 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
115 4 cycles that would be required for 2MHz operation.
116
117 See: Acorn Electron Advanced User Guide
118 See: Acorn Electron Service Manual
119 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
120 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
121 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
122
123 Bandwidth Figures
124 -----------------
125
126 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
127 total lines, with 80 cycles occurring in the active periods of display
128 scanlines, the following bandwidth calculations can be performed:
129
130 Total theoretical maximum:
131 128 cycles * 312 lines
132 = 39936 bytes
133
134 MODE 0, 1, 2:
135 ULA: 80 cycles * 256 lines
136 = 20480 bytes
137 CPU: 48 cycles / 2 * 256 lines
138 + 128 cycles / 2 * (312 - 256) lines
139 = 9728 bytes
140
141 MODE 3:
142 ULA: 80 cycles * 24 rows * 8 lines
143 = 15360 bytes
144 CPU: 48 cycles / 2 * 24 rows * 8 lines
145 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
146 = 12288 bytes
147
148 MODE 4, 5:
149 ULA: 40 cycles * 256 lines
150 = 10240 bytes
151 CPU: (40 cycles + 48 cycles / 2) * 256 lines
152 + 128 cycles / 2 * (312 - 256) lines
153 = 19968 bytes
154
155 MODE 6:
156 ULA: 40 cycles * 24 rows * 8 lines
157 = 7680 bytes
158 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
159 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
160 = 19968 bytes
161
162 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
163 only uses every other access opportunity even in uncontended periods. See the
164 2MHz RAM Access enhancement below for bandwidth calculations that consider
165 this limitation removed.
166
167 Video Timing
168 ------------
169
170 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
171 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
172 (including the "colour burst"), and 1.65µs for the "front porch", totalling
173 12.05µs and thus leaving 51.95µs for the active video signal for each
174 scanline. As the Service Manual suggests in the oscilloscope traces, the
175 display information is transmitted more or less centred within the active
176 video period since the ULA will only be providing pixel data for 40µs in each
177 scanline.
178
179 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
180 each scanline can be divided into 1024 cycles, although only 640 at most are
181 actively used to provide pixel data. Pixel data production should only occur
182 within a certain period on each scanline, approximately 262 cycles after the
183 start of hsync:
184
185 active video period = 51.95µs
186 pixel data period = 40µs
187 total silent period = 51.95µs - 40µs = 11.95µs
188 silent periods (before and after) = 11.95µs / 2 = 5.975µs
189 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
190 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
191 pixel data period start cycle = 16.375µs / 62.5ns = 262
192
193 By choosing a number divisible by 8, the RAM access mechanism can be
194 synchronised with the pixel production. Thus, 256 is a more appropriate start
195 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
196 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
197 document) occurs at cycle 0.
198
199 To summarise:
200
201 HS signal starts at cycle 0 on each horizontal scanline
202 HS signal ends approximately 4µs later at cycle 64
203 Pixel data starts approximately 12µs later at cycle 256
204
205 "Re: Electron Memory Contention" provides measurements that appear consistent
206 with these calculations.
207
208 The "vertical blanking period", meaning the period before picture information
209 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
210 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
211 lines. Thus, the first visible scanline on the first field of a frame occurs
212 half way through the 23rd scanline period measured from the start of vsync
213 (indicated by "V" in the diagrams below):
214
215 10 20 23
216 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
217 Line from 1: 0 22 3
218 Line on screen: .:::::VVVVV::::: 12233445566
219 |_________________________________________________|
220 25 line vertical blanking period
221
222 In the second field of a frame, the first visible scanline coincides with the
223 24th scanline period measured from the start of line 313 in the frame:
224
225 310 336
226 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
227 Line from 313: 0 23 4
228 Line on screen: 88:::::VVVVV:::: 11223344
229 288 | |
230 |_________________________________________________|
231 25 line vertical blanking period
232
233 In order to consider only full lines, we might consider the start of each
234 frame to occur 23 lines after the start of vsync.
235
236 Again, it is likely that pixel data production should only occur on scanlines
237 within a certain period on each frame. The "625/50" document indicates that
238 only a certain region is "safe" to use, suggesting a vertically centred region
239 with approximately 15 blank lines above and below the picture. However, the
240 "PAL TV timing and voltages" document suggests 28 blank lines above and below
241 the picture. This would centre the 256 lines within the 312 lines of each
242 field and thus provide a start of picture approximately 5.5 or 5 lines after
243 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
244
245 To summarise:
246
247 CSYNC signal starts at cycle 0
248 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
249 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
250
251 See: http://en.wikipedia.org/wiki/PAL
252 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
253 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
254 http://lipas.uwasa.fi/~f76998/video/modes/
255 See: PAL TV timing and voltages
256 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
257 See: Line Standards
258 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
259 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
260 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
261 See: Re: Electron Memory Contention
262 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
263
264 RAM Integrated Circuits
265 -----------------------
266
267 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
268 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
269 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
270 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
271 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
272
273 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
274 the Samsung-produced KM41464 series is apparently equivalent to the Texas
275 Instruments 4164 chips presumably used in the Electron.
276
277 The TM4164EC4 series combines 4 64K x 1b units into a single package and
278 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
279 (in the Advanced User Guide but not the Service Manual), and it also has 22
280 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
281 of the individual 4164-15 modules, presumably allowing concurrent access to
282 the packaged memory units.
283
284 As far as currently available replacements are concerned, the NTE4164 is a
285 potential candidate: according to the Vetco Electronics entry, it is
286 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
287 parts include the NTE2164 and the NTE6664, both of which appear to have
288 largely the same performance and connection characteristics. Meanwhile, the
289 NTE21256 appears to be a 16-pin replacement with four times the capacity that
290 maintains the single data input and output pins. Using the NTE21256 as a
291 replacement for all ICs combined would be difficult because of the single bit
292 output.
293
294 Another device equivalent to the 4164-15 appears to be available under the
295 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
296 site lists data sheets for other devices on the same page, but these are
297 different and actually appear to be provided under the 41574 product code (but
298 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
299 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
300 employing 4 pins for both input and output.
301
302 Pins I/O pins Row access Column access
303 ---- -------- ---------- -------------
304 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
305 KM41464AP 18 4 150ns (15) 75ns (15)
306 NTE21256 16 1 + 1 150ns 75ns
307 HYB 4164-2 16 1 + 1 150ns 100ns
308 µPD41464 18 4 120ns (12) 60ns (12)
309
310 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
311 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
312 See: Dynamic RAMS
313 http://www.unicornelectronics.com/IC/DYNAMIC.html
314 See: New old stock 8x 4164 chips
315 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
316 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
317 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
318 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
319 http://www.vetco.net/catalog/product_info.php?products_id=2806
320 See: NTE4164 - IC-NMOS 64K DRAM 150NS
321 http://www.vetco.net/catalog/product_info.php?products_id=3680
322 See: NTE21256 - IC-256K DRAM 150NS
323 http://www.vetco.net/catalog/product_info.php?products_id=2799
324 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
325 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
326 See: NTE6664 - IC-MOS 64K DRAM 150NS
327 http://www.vetco.net/catalog/product_info.php?products_id=5213
328 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
329 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
330 See: 4164-150: MAJOR BRANDS
331 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
332 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
333 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
334 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
335 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
336 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
337 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
338 See: 41464-10: MAJOR BRANDS
339 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
340
341 Interrupts
342 ----------
343
344 The ULA generates IRQs (maskable interrupts) according to certain conditions
345 and these conditions are controlled by location &FE00:
346
347 * Vertical sync (bottom of displayed screen)
348 * 50MHz real time clock
349 * Transmit data empty
350 * Receive data full
351 * High tone detect
352
353 The ULA is also used to clear interrupt conditions through location &FE05. Of
354 particular significance is bit 7, which must be set if an NMI (non-maskable
355 interrupt) has occurred and has thus suspended ULA access to memory, restoring
356 the normal function of the ULA.
357
358 ROM Paging
359 ----------
360
361 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
362 mappings exist:
363
364 8 keyboard
365 9 keyboard (duplicate)
366 10 BASIC ROM
367 11 BASIC ROM (duplicate)
368
369 Paging in a ROM involves the following procedure:
370
371 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
372 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
373 selected.
374 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
375 whilst writing the desired ROM number n in bits 0 to 2.
376
377 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
378
379 Shadow/Expanded Memory
380 ----------------------
381
382 The Electron exposes all sixteen address lines and all eight data lines
383 through the expansion bus. Using such lines, it is possible to provide
384 additional memory - typically sideways ROM and RAM - on expansion cards and
385 through cartridges, although the official cartridge specification provides
386 fewer address lines and only seeks to provide access to memory in 16K units.
387
388 Various modifications and upgrades were developed to offer "turbo"
389 capabilities to the Electron, permitting the CPU to access a separate 8K of
390 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
391 the ULA through additional logic. However, an enhanced ULA might support
392 independent CPU access to memory over the expansion bus by allowing itself to
393 be discharged from providing access to memory, potentially for a range of
394 addresses, and for the CPU to communicate with external memory uninterrupted.
395
396 Sideways RAM/ROM and Upper Memory Access
397 ----------------------------------------
398
399 Although the ULA controls the CPU clock, effectively slowing or stopping the
400 CPU when the ULA needs to access screen memory, it is apparently able to allow
401 the CPU to access addresses of &8000 and above - the upper region of memory -
402 at 2MHz independently of any access to RAM that the ULA might be performing,
403 only blocking the CPU if it attempts to access addresses of &7FFF and below
404 during any ULA memory access - the lower region of memory - by stopping or
405 stalling its clock.
406
407 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
408 CPU clock if the line goes low, when the CPU is attempting to access the lower
409 region of memory.
410
411 Hardware Scrolling (and Enhancement)
412 ------------------------------------
413
414 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
415 the least significant 5 bits being zero, thus limiting the scrolling
416 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
417 using the same layout of these addresses.
418
419 |--&FE02--------------| |--&FE03--------------|
420 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
421
422 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
423
424 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
425 memory to pixel locations is character oriented. A change in 8 bytes would
426 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
427 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
428 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
429 Guide).
430
431 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
432 of changing the screen address by 2 bytes is the change in the number of lines
433 from the initial and final character rows that need reading by the ULA, which
434 would need to maintain this state information (although this is a relatively
435 trivial change). Another pitfall is the complication that might be introduced
436 to software writing bitmaps of character height to the screen.
437
438 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
439
440 Enhancement: Mode Layouts
441 -------------------------
442
443 Merely changing the screen memory mappings in order to have Archimedes-style
444 row-oriented screen addresses (instead of character-oriented addresses) could
445 be done for the existing modes, but this might not be sufficiently beneficial,
446 especially since accessing regions of the screen would involve incrementing
447 pointers by amounts that are inconvenient on an 8-bit CPU.
448
449 However, instead of using a Archimedes-style mapping, column-oriented screen
450 addresses could be more feasibly employed: incrementing the address would
451 reference the vertical screen location below the currently-referenced location
452 (just as occurs within characters using the existing ULA); instead of
453 returning to the top of the character row and referencing the next horizontal
454 location after eight bytes, the address would reference the next character row
455 and continue to reference locations downwards over the height of the screen
456 until reaching the bottom; at the bottom, the next location would be the next
457 horizontal location at the top of the screen.
458
459 In other words, the memory layout for the screen would resemble the following
460 (for MODE 2):
461
462 &3000 &3100 ... &7F00
463 &3001 &3101
464 ... ...
465 &3007
466 &3008
467 ...
468 ... ...
469 &30FF ... &7FFF
470
471 Since there are 256 pixel rows, each column of locations would be addressable
472 using the low byte of the address. Meanwhile, the high byte would be
473 incremented to address different columns. Thus, addressing screen locations
474 would become a lot more convenient and potentially much more efficient for
475 certain kinds of graphical output.
476
477 One potential complication with this simplified addressing scheme arises with
478 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
479 with the existing ULA) would be achieved by incrementing or decrementing the
480 screen start address; by one character row, it would involve adding or
481 subtracting 8. However, the ULA only supports multiples of 64 when changing the
482 screen start address. Thus, if such a scheme were to be adopted, three
483 additional bits would need to be supported in the screen start register (see
484 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
485 scrolling would be much improved even under the severe constraints of the
486 existing ULA: only adjustments of 256 to the screen start address would be
487 required to produce single-location scrolling of as few as two pixels in MODE 2
488 (four pixels in MODEs 1 and 5, eight pixels otherwise).
489
490 More disruptive is the effect of this alternative layout on software.
491 Presumably, compatibility with the BBC Micro was the primary goal of the
492 Electron's hardware design. With the character-oriented screen layout in
493 place, system software (and application software accessing the screen
494 directly) would be relying on this layout to run on the Electron with little
495 or no modification. Although it might have been possible to change the system
496 software to use this column-oriented layout instead, this would have incurred
497 a development cost and caused additional work porting things like games to the
498 Electron. Moreover, a separate branch of the software from that supporting the
499 BBC Micro and closer derivatives would then have needed maintaining.
500
501 The decision to use the character-oriented layout in the BBC Micro may have
502 been related to the choice of circuitry and to facilitate a convenient
503 hardware implementation, and by the time the Electron was planned, it was too
504 late to do anything about this somewhat unfortunate choice.
505
506 Pixel Layouts
507 -------------
508
509 The pixel layouts are as follows:
510
511 Modes Depth (bpp) Pixels (from bits)
512 ----- ----------- ------------------
513 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
514 1, 5 2 73 62 51 40
515 2 4 7531 6420
516
517 Since the ULA reads a half-byte at a time, one might expect it to attempt to
518 produce pixels for every half-byte, as opposed to handling entire bytes.
519 However, the pixel layout is not conducive to producing pixels as soon as a
520 half-byte has been read for a given full-byte location: in 1bpp modes the
521 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
522 data is spread across the entire byte in different ways.
523
524 An alternative arrangement might be as follows:
525
526 Modes Depth (bpp) Pixels (from bits)
527 ----- ----------- ------------------
528 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
529 1, 5 2 76 54 32 10
530 2 4 7654 3210
531
532 Just as the mode layouts were presumably decided by compatibility with the BBC
533 Micro, the pixel layouts will have been maintained for similar reasons.
534 Unfortunately, this layout prevents any optimisation of the ULA for handling
535 half-byte pixel data generally.
536
537 Enhancement: The Missing MODE 4
538 -------------------------------
539
540 The Electron inherits its screen mode selection from the BBC Micro, where MODE
541 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
542 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
543 however, and they are merely implemented by skipping two scanlines in every
544 ten after the eight required to produce a character line. Thus, such modes
545 provide a 24-row display.
546
547 In principle, nothing prevents this "text mode" effect being applied to other
548 modes. The 20-column modes are not well-suited to displaying text, which
549 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
550 2. Although the need for a non-monochrome 40-column text mode is addressed by
551 MODE 7 on the BBC Micro, the Electron lacks such a mode.
552
553 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
554 would occupy MODE 4 instead of the current MODE 4:
555
556 Screen mode Size (kilobytes) Colours Rows Resolution
557 ----------- ---------------- ------- ---- ----------
558 0 20 2 32 640x256
559 1 20 4 32 320x256
560 2 20 16 32 160x256
561 3 16 2 24 640x256
562 4 (new) 16 4 24 320x256
563 4 (old) 10 2 32 320x256
564 5 10 4 32 160x256
565 6 8 2 24 320x256
566
567 Thus, for increasing mode numbers, the size of each mode would be the same or
568 less than the preceding mode.
569
570 Enhancement: 2MHz RAM Access
571 ----------------------------
572
573 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
574 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
575 if the ULA still needed to access the RAM), one useful enhancement would be a
576 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
577 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
578 3.
579
580 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
581
582 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
583 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
584
585 In MODE 4 to 6:
586
587 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
588 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
589
590 This would improve CPU bandwidth as follows:
591
592 Standard ULA Enhanced ULA
593 MODE 0, 1, 2 9728 bytes 19456 bytes
594 MODE 3 12288 bytes 24576 bytes
595 MODE 4, 5 19968 bytes 29696 bytes
596 MODE 6 19968 bytes 32256 bytes
597
598 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
599 because all access opportunities to RAM are doubled. Meanwhile, in the other
600 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
601 doubled, but the CPU bandwidth increase is still significant.
602
603 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
604 within the time constraints of 2MHz operation. There is no time remaining in a
605 2MHz cycle for the CPU to receive and process any retrieved data.
606
607 Enhancement: Region Blanking
608 ----------------------------
609
610 The problem of permitting character-oriented blitting in programs whilst
611 scrolling the screen by sub-character amounts could be mitigated by permitting
612 a region of the display to be blank, such as the final lines of the display.
613 Consider the following vertical scrolling by 2 bytes that would cause an
614 initial character row of 6 lines and a final character row of 2 lines:
615
616 6 lines - initial, partial character row
617 248 lines - 31 complete rows
618 2 lines - final, partial character row
619
620 If a routine were in use that wrote 8 line bitmaps to the partial character
621 row now split in two, it would be advisable to hide one of the regions in
622 order to prevent content appearing in the wrong place on screen (such as
623 content meant to appear at the top "leaking" onto the bottom). Blanking 6
624 lines would be sufficient, as can be seen from the following cases.
625
626 Scrolling up by 2 lines:
627
628 6 lines - initial, partial character row
629 240 lines - 30 complete rows
630 4 lines - part of 1 complete row
631 -----------------------------------------------------------------
632 4 lines - part of 1 complete row (hidden to maintain 250 lines)
633 2 lines - final, partial character row (hidden)
634
635 Scrolling down by 2 lines:
636
637 2 lines - initial, partial character row
638 248 lines - 31 complete rows
639 ----------------------------------------------------------
640 6 lines - final, partial character row (hidden)
641
642 Thus, in this case, region blanking would impose a 250 line display with the
643 bottom 6 lines blank.
644
645 See the description of the display suspend enhancement for a more efficient
646 way of blanking lines than merely blanking the palette whilst allowing the CPU
647 to perform useful work during the blanking period.
648
649 To control the blanking or suspending of lines at the top and bottom of the
650 display, a memory location could be dedicated to the task: the upper 4 bits
651 could define a blanking region of up to 16 lines at the top of the screen,
652 whereas the lower 4 bits could define such a region at the bottom of the
653 screen. If more lines were required, two locations could be employed, allowing
654 the top and bottom regions to occupy the entire screen.
655
656 Enhancement: Screen Height Adjustment
657 -------------------------------------
658
659 The height of the screen could be configurable in order to reduce screen
660 memory consumption. This is not quite done in MODE 3 and 6 since the start of
661 the screen appears to be rounded down to the nearest page, but by reducing the
662 height by amounts more than a page, savings would be possible. For example:
663
664 Screen width Depth Height Bytes per line Saving in bytes Start address
665 ------------ ----- ------ -------------- --------------- -------------
666 640 1 252 80 320 &3140 -> &3100
667 640 1 248 80 640 &3280 -> &3200
668 320 1 240 40 640 &5A80 -> &5A00
669 320 2 240 80 1280 &3500
670
671 Screen Mode Selection
672 ---------------------
673
674 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
675 range of modes, the other bits of &FE*7 (related to sound, cassette
676 input/output and the Caps Lock LED) would need to be reassigned and bit 0
677 potentially being made available for use.
678
679 Enhancement: Palette Definition
680 -------------------------------
681
682 Since all memory accesses go via the ULA, an enhanced ULA could employ more
683 specific addresses than &FE*X to perform enhanced functions. For example, the
684 palette control is done using &FE*8-F and merely involves selecting predefined
685 colours, whereas an enhanced ULA could support the redefinition of all 16
686 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
687 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
688 specifications similar to those used on the Archimedes.
689
690 The principal limitation here is actually the hardware: the Electron has only
691 a single output line for each of the red, green and blue channels, and if
692 those outputs are strictly digital and can only be set to a "high" and "low"
693 value, then only the existing eight colours are possible. If a modern ULA were
694 able to output analogue values (or values at well-defined points between the
695 high and low values, such as the half-on value supported by the Amstrad CPC
696 series), it would still need to be assessed whether the circuitry could
697 successfully handle and propagate such values. Various sources indicate that
698 only "TTL levels" are supported by the RGB output circuit, and since there are
699 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
700 is likely that the ULA is expected to provide only "high" or "low" values.
701
702 Short of adding extra outputs from the ULA (either additional red, green and
703 blue outputs or a combined intensity output), another approach might involve
704 some kind of modulation where an output value might be encoded in multiple
705 pulses at a higher frequency than the pixel frequency. However, this would
706 demand additional circuitry outside the ULA, and component RGB monitors would
707 probably not be able to take advantage of this feature; only UHF and composite
708 video devices (the latter with the composite video colour support enabled on
709 the Electron's circuit board) would potentially benefit.
710
711 Flashing Colours
712 ----------------
713
714 According to the Advanced User Guide, "The cursor and flashing colours are
715 entirely generated in software: This means that all of the logical to physical
716 colour map must be changed to cause colours to flash." This appears to suggest
717 that the palette registers must be updated upon the flash counter - read and
718 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
719 colour pairs to be any combination of colours might be possible, instead of
720 having colour complements as pairs.
721
722 It is conceivable that the interrupt code responsible does the simple thing
723 and merely inverts the current values for any logical colours (LC) for which
724 the associated physical colour (as supplied as the second parameter to the VDU
725 19 call) has the top bit of its four bit value set. These top bits are not
726 recorded in the palette registers but are presumably recorded separately and
727 used to build bitmaps as follows:
728
729 LC 2 colour 4 colour 16 colour 4-bit value for inversion
730 -- -------- -------- --------- -------------------------
731 0 00010001 00010001 00010001 1, 1, 1
732 1 01000100 00100010 00010001 4, 2, 1
733 2 01000100 00100010 4, 2
734 3 10001000 00100010 8, 2
735 4 00010001 1
736 5 00010001 1
737 6 00100010 2
738 7 00100010 2
739 8 01000100 4
740 9 01000100 4
741 10 10001000 8
742 11 10001000 8
743 12 01000100 4
744 13 01000100 4
745 14 10001000 8
746 15 10001000 8
747
748 Inversion value calculation:
749
750 2 colour formula: 1 << (colour * 2)
751 4 colour formula: 1 << colour
752 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
753
754 For example, where logical colour 0 has been mapped to a physical colour in
755 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
756 the inversion operation. (The lower three bits of the physical colour would be
757 used to set the underlying colour information affected by the inversion
758 operation.)
759
760 An operation in the interrupt code would then combine the bitmaps for all
761 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
762 combined for groups of logical colours as follows:
763
764 Logical colours
765 ---------------
766 0, 2, 8, 10
767 4, 6, 12, 14
768 5, 7, 13, 15
769 1, 3, 9, 11
770
771 These combined bitmaps would be EORed with the existing palette register
772 values in order to perform the value inversion necessary to produce the
773 flashing effect.
774
775 Thus, in the VDU 19 operation, the appropriate inversion value would be
776 calculated for the logical colour, and this value would then be combined with
777 other inversion values in a dedicated memory location corresponding to the
778 colour's group as indicated above. Meanwhile, the palette channel values would
779 be derived from the lower three bits of the specified physical colour and
780 combined with other palette data in dedicated memory locations corresponding
781 to the palette registers.
782
783 Interestingly, although flashing colours on the BBC Micro are controlled by
784 toggling bit 0 of the &FE20 control register location for the Video ULA, the
785 actual colour inversion is done in hardware.
786
787 Enhancement: Palette Definition Lists
788 -------------------------------------
789
790 It can be useful to redefine the palette in order to change the colours
791 available for a particular region of the screen, particularly in modes where
792 the choice of colours is constrained, and if an increased colour depth were
793 available, palette redefinition would be useful to give the illusion of more
794 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
795 by using interrupt-driven timers, but a more efficient approach would involve
796 presenting lists of palette definitions to the ULA so that it can change the
797 palette at a particular display line.
798
799 One might define a palette redefinition list in a region of memory and then
800 communicate its contents to the ULA by writing the address and length of the
801 list, along with the display line at which the palette is to be changed, to
802 ULA registers such that the ULA buffers the list and performs the redefinition
803 at the appropriate time. Throughput/bandwidth considerations might impose
804 restrictions on the practical length of such a list, however.
805
806 Enhancement: Display Synchronisation Interrupts
807 -----------------------------------------------
808
809 When completing each scanline of the display, the ULA could trigger an
810 interrupt. Since this might impact system performance substantially, the
811 feature would probably need to be configurable, and it might be sufficient to
812 have an interrupt only after a certain number of display lines instead.
813 Permitting the CPU to take action after eight lines would allow palette
814 switching and other effects to occur on a character row basis.
815
816 The ULA provides an interrupt at the end of the display period, presumably so
817 that software can schedule updates to the screen, avoid flickering or tearing,
818 and so on. However, some applications might benefit from an interrupt at, or
819 just before, the start of the display period so that palette modifications or
820 similar effects could be scheduled.
821
822 Enhancement: Palette-Free Modes
823 -------------------------------
824
825 Palette-free modes might be defined where bit values directly correspond to
826 the red, green and blue channels, although this would mostly make sense only
827 for modes with depths greater than the standard 4 bits per pixel, and such
828 modes would require more memory than MODE 2 if they were to have an acceptable
829 resolution.
830
831 Enhancement: Display Suspend
832 ----------------------------
833
834 Especially when writing to the screen memory, it could be beneficial to be
835 able to suspend the ULA's access to the memory, instead producing blank values
836 for all screen pixels until a program is ready to reveal the screen. This is
837 different from palette blanking since with a blank palette, the ULA is still
838 reading screen memory and translating its contents into pixel values that end
839 up being blank.
840
841 This function is reminiscent of a capability of the ZX81, albeit necessary on
842 that hardware to reduce the load on the system CPU which was responsible for
843 producing the video output. By allowing display suspend on the Electron, the
844 performance benefit would be derived from giving the CPU full access to the
845 memory bandwidth.
846
847 The region blanking feature mentioned above could be implemented using this
848 enhancement instead of employing palette blanking for the affected lines of
849 the display.
850
851 Enhancement: Memory Filling
852 ---------------------------
853
854 A capability that could be given to an enhanced ULA is that of permitting the
855 ULA to write to screen memory as well being able to read from it. Although
856 such a capability would probably not be useful in conjunction with the
857 existing read operations when producing a screen display, and insufficient
858 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
859 capability could be offered during a display suspend period (as described
860 above), permitting a more efficient mechanism to rapidly fill memory with a
861 predetermined value.
862
863 This capability could also support block filling, where the limits of the
864 filled memory would be defined by the position and size of a screen area,
865 although this would demand the provision of additional registers in the ULA to
866 retain the details of such areas and additional logic to control the fill
867 operation.
868
869 Enhancement: Region Filling
870 ---------------------------
871
872 An alternative to memory writing might involve indicating regions using
873 additional registers or memory where the ULA fills regions of the screen with
874 content instead of reading from memory. Unlike hardware sprites which should
875 realistically provide varied content, region filling could employ single
876 colours or patterns, and one advantage of doing so would be that the ULA need
877 not access memory at all within a particular region.
878
879 Regions would be defined on a row-by-row basis. Instead of reading memory and
880 blitting a direct representation to the screen, the ULA would read region
881 definitions containing a start column, region width and colour details. There
882 might be a certain number of definitions allowed per row, or the ULA might
883 just traverse an ordered list of such definitions with each one indicating the
884 row, start column, region width and colour details.
885
886 One could even compress this information further by requiring only the row,
887 start column and colour details with each subsequent definition terminating
888 the effect of the previous one. However, one would also need to consider the
889 convenience of preparing such definitions and whether efficient access to
890 definitions for a particular row might be desirable. It might also be
891 desirable to avoid having to prepare definitions for "empty" areas of the
892 screen, effectively making the definition of the screen contents employ
893 run-length encoding and employ only colour plus length information.
894
895 One application of region filling is that of simple 2D and 3D shape rendering.
896 Although it is entirely possible to plot such shapes to the screen and have
897 the ULA blit the memory contents to the screen, such operations consume
898 bandwidth both in the initial plotting and in the final transfer to the
899 screen. Region filling would reduce such bandwidth usage substantially.
900
901 This way of representing screen images would make certain kinds of images
902 unfeasible to represent - consider alternating single pixel values which could
903 easily occur in some character bitmaps - even if an internal queue of regions
904 were to be supported such that the ULA could read ahead and buffer such
905 "bandwidth intensive" areas. Thus, the ULA might be better served providing
906 this feature for certain areas of the display only as some kind of special
907 graphics window.
908
909 Enhancement: Hardware Sprites
910 -----------------------------
911
912 An enhanced ULA might provide hardware sprites, but this would be done in an
913 way that is incompatible with the standard ULA, since no &FE*X locations are
914 available for allocation. To keep the facility simple, hardware sprites would
915 have a standard byte width and height.
916
917 The specification of sprites could involve the reservation of 16 locations
918 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
919 location pair referring to the sprite data. By limiting the ULA to dealing
920 with a fixed number of sprites, the work required inside the ULA would be
921 reduced since it would avoid having to deal with arbitrary numbers of sprites.
922
923 The principal limitation on providing hardware sprites is that of having to
924 obtain sprite data, given that the ULA is usually required to retrieve screen
925 data, and given the lack of memory bandwidth available to retrieve sprite data
926 (particularly from multiple sprites supposedly at the same position) and
927 screen data simultaneously. Although the ULA could potentially read sprite
928 data and screen data in alternate memory accesses in screen modes where the
929 bandwidth is not already fully utilised, this would result in a degradation of
930 performance.
931
932 Enhancement: Additional Screen Mode Configurations
933 --------------------------------------------------
934
935 Alternative screen mode configurations could be supported. The ULA has to
936 produce 640 pixel values across the screen, with pixel doubling or quadrupling
937 employed to fill the screen width:
938
939 Screen width Columns Scaling Depth Bytes
940 ------------ ------- ------- ----- -----
941 640 80 x1 1 80
942 320 40 x2 1, 2 40, 80
943 160 20 x4 2, 4 40, 80
944
945 It must also use at most 80 byte-sized memory accesses to provide the
946 information for the display. Given that characters must occupy an 8x8 pixel
947 array, if a configuration featuring anything other than 20, 40 or 80 character
948 columns is to be supported, compromises must be made such as the introduction
949 of blank pixels either between characters (such as occurs between rows in MODE
950 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
951 in MODE 3 and 6). Consider the following configuration:
952
953 Screen width Columns Scaling Depth Bytes Blank
954 ------------ ------- ------- ----- ------ -----
955 208 26 x3 1, 2 26, 52 16
956
957 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
958 colours could be provided, with 16 blank pixel values (out of a total of 640)
959 generated either at the start or end (or split between the start and end) of
960 each scanline.
961
962 Enhancement: Character Attributes
963 ---------------------------------
964
965 The BBC Micro MODE 7 employs something resembling character attributes to
966 support teletext displays, but depends on circuitry providing a character
967 generator. The ZX Spectrum, on the other hand, provides character attributes
968 as a means of colouring bitmapped graphics. Although such a feature is very
969 limiting as the sole means of providing multicolour graphics, in situations
970 where the choice is between low resolution multicolour graphics or high
971 resolution monochrome graphics, character attributes provide a potentially
972 useful compromise.
973
974 For each byte read, the ULA must deliver 8 pixel values (out of a total of
975 640) to the video output, doing so by either emptying its pixel buffer on a
976 pixel per cycle basis, or by multiplying pixels and thus holding them for more
977 than one cycle. For example for a screen mode having 640 pixels in width:
978
979 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
980 Reads: B B
981 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
982
983 And for a screen mode having 320 pixels in width:
984
985 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
986 Reads: B
987 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
988
989 However, in modes where less than 80 bytes are required to generate the pixel
990 values, an enhanced ULA might be able to read additional bytes between those
991 providing the bitmapped graphics data:
992
993 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
994 Reads: B A
995 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
996
997 These additional bytes could provide colour information for the bitmapped data
998 in the following character column (of 8 pixels). Since it would be desirable
999 to apply attribute data to the first column, the initial 8 cycles might be
1000 configured to not produce pixel values.
1001
1002 For an entire character, attribute data need only be read for the first row of
1003 pixels for a character. The subsequent rows would have attribute information
1004 applied to them, although this would require the attribute data to be stored
1005 in some kind of buffer. Thus, the following access pattern would be observed:
1006
1007 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
1008
1009 A whole byte used for colour information for a whole character would result in
1010 a choice of 256 colours, and this might be somewhat excessive. By only reading
1011 attribute bytes at every other opportunity, a choice of 16 colours could be
1012 applied individually to two characters.
1013
1014 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1015 Reads: B A B -
1016 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1017
1018 Further reductions in attribute data access, offering 4 colours for every
1019 character in a four character block, for example, might also be worth
1020 considering.
1021
1022 Consider the following configurations for screen modes with a colour depth of
1023 1 bit per pixel for bitmap information:
1024
1025 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1026 ------------ ------- ------- --------- --------- ------- ------------
1027 320 40 x2 40 40 256 &5300
1028 320 40 x2 40 20 16 &5580 -> &5500
1029 320 40 x2 40 10 4 &56C0 -> &5600
1030 208 26 x3 26 26 256 &62C0 -> &6200
1031 208 26 x3 26 13 16 &6460 -> &6400
1032
1033 Enhancement: MODE 7 Emulation using Character Attributes
1034 --------------------------------------------------------
1035
1036 If the scheme of applying attributes to character regions were employed to
1037 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1038 following configuration would be required:
1039
1040 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1041 ------------ ------- ---- --------- --------- ------- ------------
1042 320 40 25 40 20 16 &5ECC -> &5E00
1043 320 40 25 40 10 4 &5FC6 -> &5F00
1044
1045 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1046 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1047 at least make a limited 40-column multicolour mode available as a substitute
1048 for MODE 7.
1049
1050 Enhancement: High Resolution Graphics
1051 -------------------------------------
1052
1053 Screen modes with higher resolutions and larger colour depths might be
1054 possible, but this would in most cases involve the allocation of more screen
1055 memory, and the ULA would probably then be obliged to page in such memory for
1056 the CPU to be able to sensibly access it all.
1057
1058 Enhancement: Genlock Support
1059 ----------------------------
1060
1061 The ULA generates a video signal in conjunction with circuitry producing the
1062 output features necessary for the correct display of the screen image.
1063 However, it appears that the ULA drives the video synchronisation mechanism
1064 instead of reacting to an existing signal. Genlock support might be possible
1065 if the ULA were made to be responsive to such external signals, resetting its
1066 address generators upon receiving synchronisation events.
1067
1068 Enhancement: Improved Sound
1069 ---------------------------
1070
1071 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1072 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1073 cassette I/O), thus making it impossible to support multiple channels within
1074 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1075 and an enhanced ULA could adopt this interface.
1076
1077 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1078 functionality of this chip could be emulated for enhanced sound, with a subset
1079 of the functionality exposed via the &FE*6 interface.
1080
1081 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1082 See: http://www.smspower.org/Development/SN76489
1083
1084 Enhancement: Waveform Upload
1085 ----------------------------
1086
1087 As with a hardware sprite function, waveforms could be uploaded or referenced
1088 using locations as registers referencing memory regions.
1089
1090 Enhancement: Sound Input/Output
1091 -------------------------------
1092
1093 Since the ULA already controls audio input/output for cassette-based data, it
1094 would have been interesting to entertain the idea of sampling and output of
1095 sounds through the cassette interface. However, a significant amount of
1096 circuitry is employed to process the input signal for use by the ULA and to
1097 process the output signal for recording.
1098
1099 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1100
1101 Enhancement: BBC ULA Compatibility
1102 ----------------------------------
1103
1104 Although some new ULA functions could be defined in a way that is also
1105 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1106 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1107 map, but controls various functions specific to the 6845 video controller;
1108 &FE08-F is reserved for the serial controller. It therefore becomes possible
1109 to disregard compatibility where compatibility is already disregarded for a
1110 particular area of functionality.
1111
1112 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1113 control over the palette (using address &FE21, compared to &FE07-F on the
1114 Electron) and other system-specific functions. Since the location usage is
1115 generally incompatible, this region could be reused for other purposes.
1116
1117 Enhancement: Increased RAM, ULA and CPU Performance
1118 ---------------------------------------------------
1119
1120 More modern implementations of the hardware might feature faster RAM coupled
1121 with an increased ULA clock frequency in order to increase the bandwidth
1122 available to the ULA and to the CPU in situations where the ULA is not needed
1123 to perform work. A ULA employing a 32MHz clock would be able to complete the
1124 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1125 to access the RAM for the following 250ns even in display modes requiring the
1126 retrieval of a byte for the display every 500ns. The CPU could, subject to
1127 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1128
1129 A scheme such as that described above would have a similar effect to the
1130 scheme employed in the BBC Micro, although the latter made use of RAM with a
1131 wider bandwidth in order to complete memory transfers within 250ns and thus
1132 permit the CPU to run continuously at 2MHz.
1133
1134 Higher bandwidth could potentially be used to implement exotic features such
1135 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1136 concurrent with the production of the display image.
1137
1138 Enhancement: Multiple CPU Stacks and Zero Pages
1139 -----------------------------------------------
1140
1141 The 6502 maintains a stack for subroutine calls and register storage in page
1142 &01. Although the stack register can be manipulated using the TSX and TXS
1143 instructions, thereby permitting the maintenance of multiple stack regions and
1144 thus the potential coexistence of multiple programs each using a separate
1145 region, only programs that make little use of the stack (perhaps avoiding
1146 deeply-nested subroutine invocations and significant register storage) would
1147 be able to coexist without overwriting each other's stacks.
1148
1149 One way that this issue could be alleviated would involve the provision of a
1150 facility to redirect accesses to page &01 to other areas of memory. The ULA
1151 would provide a register that defines a physical page for the use of the CPU's
1152 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1153 change the asserted address lines to redirect the access to the appropriate
1154 physical region.
1155
1156 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1157 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1158 register value before the access is made. Where multiple programs coexist,
1159 upon switching programs, the register would be updated to point the ULA to the
1160 appropriate stack location, thus providing a simple memory management unit
1161 (MMU) capability.
1162
1163 In a similar fashion, zero page accesses could also be redirected so that code
1164 could run from sideways RAM and have zero page operations redirected to "upper
1165 memory" - for example, to page &BE (with stack accesses redirected to page
1166 &BF, perhaps) - thereby permitting most CPU operations to occur without
1167 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1168 CPU as it contends with the ULA for memory access.
1169
1170 Such facilities could also be provided by a separate circuit between the CPU
1171 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1172 such boards, no additional RAM would be provided: all memory accesses would
1173 occur as normal through the ULA, albeit redirected when configured
1174 appropriately.
1175
1176 ULA Pin Functions
1177 -----------------
1178
1179 The functions of the ULA pins are described in the Electron Service Manual. Of
1180 interest to video processing are the following:
1181
1182 CSYNC (low during horizontal or vertical synchronisation periods, high
1183 otherwise)
1184
1185 HS (low during horizontal synchronisation periods, high otherwise)
1186
1187 RED, GREEN, BLUE (pixel colour outputs)
1188
1189 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1190
1191 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1192
1193 More general memory access pins:
1194
1195 RAM0...RAM3 (data lines to/from the RAM)
1196
1197 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1198
1199 RAS (row address strobe setting the row address on a negative edge - see the
1200 timing notes)
1201
1202 CAS (column address strobe setting the column address on a negative edge -
1203 see the timing notes)
1204
1205 WE (sets write enable with logic 0, read with logic 1)
1206
1207 ROM (select data access from ROM)
1208
1209 CPU-oriented memory access pins:
1210
1211 A0...A15 (CPU address lines)
1212
1213 PD0...PD7 (CPU data lines)
1214
1215 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1216
1217 Interrupt-related pins:
1218
1219 NMI (CPU request for uninterrupted 1MHz access to memory)
1220
1221 IRQ (signal event to CPU)
1222
1223 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1224 CPU's RST pin)
1225
1226 RST (master reset for the CPU signalled on power-up and by the Break key)
1227
1228 Keyboard-related pins:
1229
1230 KBD0...KBD3 (keyboard inputs)
1231
1232 CAPS LOCK (control status LED)
1233
1234 Sound-related pins:
1235
1236 SOUND O/P (sound output using internal oscillator)
1237
1238 Cassette-related pins:
1239
1240 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1241
1242 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1243
1244 CAS RC (detect high tone)
1245
1246 CAS MO (motor relay output)
1247
1248 ÷13 IN (~1200 baud clock input)
1249
1250 ULA Socket
1251 ----------
1252
1253 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1254
1255 References
1256 ----------
1257
1258 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1259
1260 About this Document
1261 -------------------
1262
1263 The most recent version of this document and accompanying distribution should
1264 be available from the following location:
1265
1266 http://hgweb.boddie.org.uk/ULA
1267
1268 Copyright and licence information can be found in the docs directory of this
1269 distribution - see docs/COPYING.txt for more information.