1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited by the amount of time and resources that
8 can be allocated to each activity necessary to support such features given the
9 fundamental obligations of the unit. Maintaining a screen display based on the
10 contents of RAM itself requires the ULA to have exclusive access to such
11 hardware resources for a significant period of time. Whilst other elements of
12 the ULA can in principle run in parallel with this activity, they cannot also
13 access the RAM. Consequently, other features that might use the RAM must
14 accept a reduced allocation of that resource in comparison to a hypothetical
15 architecture where concurrent RAM access is possible.
16
17 Thus, the principal constraint for many features is bandwidth. The duration of
18 access to hardware resources is one aspect of this; the rate at which such
19 resources can be accessed is another. For example, the RAM is not fast enough
20 to support access more frequently than one byte per 2MHz cycle, and for screen
21 modes involving 80 bytes of screen data per scanline, there are no free cycles
22 for anything other than the production of pixel output during the active
23 scanline periods.
24
25 Timing
26 ------
27
28 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
29 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
30 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
31 312 ~= 128 cycles). This is consistent with the observation that each scanline
32 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
33 out of 64 microseconds in each scanline.
34
35 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
36 each providing two bits of each byte) using two cycles within the 500ns period
37 of the 2MHz clock to complete each access operation. Since the CPU and ULA
38 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
39 effectively run at 1MHz (since every other 500ns period involves the ULA
40 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
41 frequency is divided by the ULA (IC1) depending on the screen mode in use.
42
43 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
44 patterns corresponding to 16MHz cycles are required:
45
46 Time (ns): 0-------------- 500------------ ...
47 2 MHz cycle: 0 1 ...
48 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
49 ~RAS: 0 1 0 1 ...
50 ~CAS: 0 1 0 1 0 1 0 1 ...
51 A B C A B C ...
52 F S F S ...
53 a b c a b c ...
54
55 Here, "A" and "B" respectively indicate the row and first column addresses
56 being latched into the RAM (on a negative edge for ~RAS and ~CAS
57 respectively), and "C" indicates the second column address being latched into
58 the RAM. Presumably, the first and second half-bytes can be read at "F" and
59 "S" respectively, and the row and column addresses must be made available at
60 "a" and "b" (and "c") respectively at the latest.
61
62 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
63 address access time of 90ns (maximum), which appears to mean that
64 approximately two 16MHz cycles after the row address is latched, and one and a
65 half cycles after the column address is latched, the data becomes available.
66
67 Note that the Service Manual refers to the negative edge of RAS and CAS, but
68 the datasheet for the similar TM4164EC4 product shows latching on the negative
69 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
70 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
71 "page mode" provides the appropriate behaviour for that particular product.
72
73 See: Acorn Electron Advanced User Guide
74 See: Acorn Electron Service Manual
75 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
76 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
77
78 Video Timing
79 ------------
80
81 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
82 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
83 (including the "colour burst"), and 1.65µs for the "front porch", totalling
84 12.05µs and thus leaving 51.95µs for the active video signal for each
85 scanline. As the Service Manual suggests in the oscilloscope traces, the
86 display information is transmitted more or less centred within the active
87 video period since the ULA will only be providing pixel data for 40µs in each
88 scanline.
89
90 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
91 each scanline can be divided into 1024 cycles, although only 640 at most are
92 actively used to provide pixel data. Pixel data production should only occur
93 within a certain period on each scanline, approximately 262 cycles after the
94 start of hsync:
95
96 active video period = 51.95µs
97 pixel data period = 40µs
98 total silent period = 51.95µs - 40µs = 11.95µs
99 silent periods (before and after) = 11.95µs / 2 = 5.975µs
100 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
101 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
102 pixel data period start cycle = 16.375µs / 62.5ns = 262
103
104 By choosing a number divisible by 8, the RAM access mechanism can be
105 synchronised with the pixel production. Thus, 264 is a more appropriate start
106 cycle.
107
108 The "vertical blanking period", meaning the period before picture information
109 in each field is 25 lines out of 312 (strictly 312.5) and thus lasts for
110 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts
111 for 2.5 lines. Thus, the first visible scanline on the first field of a frame
112 occurs half way through the 23rd scanline period measured from the start of
113 vsync:
114
115 10 20 23
116 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
117 Line from 1: 0 22 3
118 Line on screen: .:::::VVVVV::::: 12233445566
119 |_________________________________________________|
120 25 line vertical blanking period
121
122 In the second field of a frame, the first visible scanline coincides with the
123 24th scanline period measured from the start of line 313 in the frame:
124
125 310 336
126 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
127 Line from 313: 0 23
128 Line on screen: 88:::::VVVVV:::: 11223344
129 288 | |
130 |_________________________________________________|
131 25 line vertical blanking period
132
133 In order to consider only full lines, we might consider the start of each
134 frame to occur 23 lines after the start of vsync.
135
136 Again, it is likely that pixel data production should only occur on scanlines
137 within a certain period on each frame. The "625/50" document indicates that
138 only a certain region is "safe" to use, suggesting a vertically centred region
139 with approximately 15 blank lines above and below the picture. Thus, the start
140 of the picture could be chosen as 38 lines after the start of vsync.
141
142 See: http://en.wikipedia.org/wiki/PAL
143 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
144 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
145 http://lipas.uwasa.fi/~f76998/video/modes/
146 See: PAL TV timing and voltages
147 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
148 See: Line Standards
149 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
150
151 RAM Integrated Circuits
152 -----------------------
153
154 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
155 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
156 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
157 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
158 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
159
160 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
161 the Samsung-produced KM41464 series is apparently equivalent to the Texas
162 Instruments 4164 chips presumably used in the Electron.
163
164 The TM4164EC4 series combines 4 64K x 1b units into a single package and
165 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
166 (in the Advanced User Guide but not the Service Manual), and it also has 22
167 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
168 of the individual 4164-15 modules, presumably allowing concurrent access to
169 the packaged memory units.
170
171 As far as currently available replacements are concerned, the NTE4164 is a
172 potential candidate: according to the Vetco Electronics entry, it is
173 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
174 parts include the NTE2164 and the NTE6664, both of which appear to have
175 largely the same performance and connection characteristics. Meanwhile, the
176 NTE21256 appears to be a 16-pin replacement with four times the capacity that
177 maintains the single data input and output pins. Using the NTE21256 as a
178 replacement for all ICs combined would be difficult because of the single bit
179 output.
180
181 Another device equivalent to the 4164-15 appears to be available under the
182 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
183 site lists data sheets for other devices on the same page, but these are
184 different and actually appear to be provided under the 41574 product code (but
185 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
186 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
187 employing 4 pins for both input and output.
188
189 Pins I/O pins Row access Column access
190 ---- -------- ---------- -------------
191 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
192 KM41464AP 18 4 150ns (15) 75ns (15)
193 NTE21256 16 1 + 1 150ns 75ns
194 HYB 4164-2 16 1 + 1 150ns 100ns
195 µPD41464 18 4 120ns (12) 60ns (12)
196
197 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
198 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
199 See: Dynamic RAMS
200 http://www.unicornelectronics.com/IC/DYNAMIC.html
201 See: New old stock 8x 4164 chips
202 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
203 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
204 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
205 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
206 http://www.vetco.net/catalog/product_info.php?products_id=2806
207 See: NTE4164 - IC-NMOS 64K DRAM 150NS
208 http://www.vetco.net/catalog/product_info.php?products_id=3680
209 See: NTE21256 - IC-256K DRAM 150NS
210 http://www.vetco.net/catalog/product_info.php?products_id=2799
211 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
212 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
213 See: NTE6664 - IC-MOS 64K DRAM 150NS
214 http://www.vetco.net/catalog/product_info.php?products_id=5213
215 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
216 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
217 See: 4164-150: MAJOR BRANDS
218 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
219 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
220 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
221 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
222 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
223 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
224 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
225 See: 41464-10: MAJOR BRANDS
226 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
227
228 Interrupts
229 ----------
230
231 The ULA generates IRQs (maskable interrupts) according to certain conditions
232 and these conditions are controlled by location &FE00:
233
234 * Vertical sync (bottom of displayed screen)
235 * 50MHz real time clock
236 * Transmit data empty
237 * Receive data full
238 * High tone detect
239
240 The ULA is also used to clear interrupt conditions through location &FE05. Of
241 particular significance is bit 7, which must be set if an NMI (non-maskable
242 interrupt) has occurred and has thus suspended ULA access to memory, restoring
243 the normal function of the ULA.
244
245 ROM Paging
246 ----------
247
248 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
249 mappings exist:
250
251 8 keyboard
252 9 keyboard (duplicate)
253 10 BASIC ROM
254 11 BASIC ROM (duplicate)
255
256 Paging in a ROM involves the following procedure:
257
258 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
259 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
260 selected.
261 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
262 whilst writing the desired ROM number n in bits 0 to 2.
263
264 Shadow/Expanded Memory
265 ----------------------
266
267 The Electron exposes all sixteen address lines and all eight data lines
268 through the expansion bus. Using such lines, it is possible to provide
269 additional memory - typically sideways ROM and RAM - on expansion cards and
270 through cartridges, although the official cartridge specification provides
271 fewer address lines and only seeks to provide access to memory in 16K units.
272
273 Various modifications and upgrades were developed to offer "turbo"
274 capabilities to the Electron, permitting the CPU to access a separate 8K of
275 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
276 the ULA through additional logic. However, an enhanced ULA might support
277 independent CPU access to memory over the expansion bus by allowing itself to
278 be discharged from providing access to memory, potentially for a range of
279 addresses, and for the CPU to communicate with external memory uninterrupted.
280
281 Sideways RAM/ROM and Upper Memory Access
282 ----------------------------------------
283
284 Although the ULA controls the CPU clock, effectively slowing or stopping the
285 CPU when the ULA needs to access screen memory, it is apparently able to allow
286 the CPU to access addresses of &8000 and above - the upper region of memory -
287 at 2MHz independently of any access to RAM that the ULA might be performing,
288 only blocking the CPU if it attempts to access addresses of &7FFF and below
289 during any ULA memory access - the lower region of memory - by stopping or
290 stalling its clock.
291
292 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
293 CPU clock if the line goes low, when the CPU is attempting to access the lower
294 region of memory.
295
296 Hardware Scrolling
297 ------------------
298
299 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
300 the least significant 5 bits being zero, thus limiting the scrolling
301 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
302 using the same layout of these addresses.
303
304 |--&FE02--------------| |--&FE03--------------|
305 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
306
307 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
308
309 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
310 memory to pixel locations is character oriented. A change in 8 bytes would
311 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
312 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
313 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
314 Guide).
315
316 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
317 of changing the screen address by 2 bytes is the change in the number of lines
318 from the initial and final character rows that need reading by the ULA, which
319 would need to maintain this state information (although this is a relatively
320 trivial change). Another pitfall is the complication that might be introduced
321 to software writing bitmaps of character height to the screen.
322
323 Enhancement: Region Blanking
324 ----------------------------
325
326 The problem of permitting character-oriented blitting in programs whilst
327 scrolling the screen by sub-character amounts could be mitigated by permitting
328 a region of the display to be blank, such as the final lines of the display.
329 Consider the following vertical scrolling by 2 bytes that would cause an
330 initial character row of 6 lines and a final character row of 2 lines:
331
332 6 lines - initial, partial character row
333 248 lines - 31 complete rows
334 2 lines - final, partial character row
335
336 If a routine were in use that wrote 8 line bitmaps to the partial character
337 row now split in two, it would be advisable to hide one of the regions in
338 order to prevent content appearing in the wrong place on screen (such as
339 content meant to appear at the top "leaking" onto the bottom). Blanking 6
340 lines would be sufficient, as can be seen from the following cases.
341
342 Scrolling up by 2 lines:
343
344 6 lines - initial, partial character row
345 240 lines - 30 complete rows
346 4 lines - part of 1 complete row
347 -----------------------------------------------------------------
348 4 lines - part of 1 complete row (hidden to maintain 250 lines)
349 2 lines - final, partial character row (hidden)
350
351 Scrolling down by 2 lines:
352
353 2 lines - initial, partial character row
354 248 lines - 31 complete rows
355 ----------------------------------------------------------
356 6 lines - final, partial character row (hidden)
357
358 Thus, in this case, region blanking would impose a 250 line display with the
359 bottom 6 lines blank.
360
361 See the description of the display suspend enhancement for a more efficient
362 way of blanking lines than merely blanking the palette whilst allowing the CPU
363 to perform useful work during the blanking period.
364
365 To control the blanking or suspending of lines at the top and bottom of the
366 display, a memory location could be dedicated to the task: the upper 4 bits
367 could define a blanking region of up to 16 lines at the top of the screen,
368 whereas the lower 4 bits could define such a region at the bottom of the
369 screen. If more lines were required, two locations could be employed, allowing
370 the top and bottom regions to occupy the entire screen.
371
372 Enhancement: Screen Height Adjustment
373 -------------------------------------
374
375 The height of the screen could be configurable in order to reduce screen
376 memory consumption. This is not quite done in MODE 3 and 6 since the start of
377 the screen appears to be rounded down to the nearest page, but by reducing the
378 height by amounts more than a page, savings would be possible. For example:
379
380 Screen width Depth Height Bytes per line Saving in bytes Start address
381 ------------ ----- ------ -------------- --------------- -------------
382 640 1 252 80 320 &3140 -> &3100
383 640 1 248 80 640 &3280 -> &3200
384 320 1 240 40 640 &5A80 -> &5A00
385 320 2 240 80 1280 &3500
386
387 Screen Mode Selection
388 ---------------------
389
390 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
391 range of modes, the other bits of &FE*7 (related to sound, cassette
392 input/output and the Caps Lock LED) would need to be reassigned and bit 0
393 potentially being made available for use.
394
395 Enhancement: Palette Definition
396 -------------------------------
397
398 Since all memory accesses go via the ULA, an enhanced ULA could employ more
399 specific addresses than &FE*X to perform enhanced functions. For example, the
400 palette control is done using &FE*8-F and merely involves selecting predefined
401 colours, whereas an enhanced ULA could support the redefinition of all 16
402 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
403 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
404 specifications similar to those used on the Archimedes.
405
406 The principal limitation here is actually the hardware: the Electron has only
407 a single output line for each of the red, green and blue channels, and if
408 those outputs are strictly digital and can only be set to a "high" and "low"
409 value, then only the existing eight colours are possible. If a modern ULA were
410 able to output analogue values, it would still need to be assessed whether the
411 circuitry could successfully handle and propagate such values. Various sources
412 indicate that only "TTL levels" are supported by the RGB output circuit, and
413 since there are 74LS08 AND logic gates involved in the RGB component outputs
414 from the ULA, it is likely that the ULA is expected to provide only "high" or
415 "low" values.
416
417 Short of adding extra outputs from the ULA (either additional red, green and
418 blue outputs or a combined intensity output, the former employed on the
419 Amstrad CPC series), another approach might involve some kind of modulation
420 where an output value might be encoded in multiple pulses at a higher
421 frequency than the pixel frequency. However, this would demand additional
422 circuitry outside the ULA, and component RGB monitors would probably not be
423 able to take advantage of this feature; only UHF and composite video devices
424 (the latter with the composite video colour support enabled on the Electron's
425 circuit board) would potentially benefit.
426
427 Flashing Colours
428 ----------------
429
430 According to the Advanced User Guide, "The cursor and flashing colours are
431 entirely generated in software: This means that all of the logical to physical
432 colour map must be changed to cause colours to flash." This appears to suggest
433 that the palette registers must be updated upon the flash counter - read and
434 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
435 colour pairs to be any combination of colours might be possible, instead of
436 having colour complements as pairs.
437
438 It is conceivable that the interrupt code responsible does the simple thing
439 and merely inverts the current values for any logical colours (LC) for which
440 the associated physical colour (as supplied as the second parameter to the VDU
441 19 call) has the top bit of its four bit value set. These top bits are not
442 recorded in the palette registers but are presumably recorded separately and
443 used to build bitmaps as follows:
444
445 LC 2 colour 4 colour 16 colour 4-bit value for inversion
446 -- -------- -------- --------- -------------------------
447 0 00010001 00010001 00010001 1, 1, 1
448 1 01000100 00100010 00010001 4, 2, 1
449 2 01000100 00100010 4, 2
450 3 10001000 00100010 8, 2
451 4 00010001 1
452 5 00010001 1
453 6 00100010 2
454 7 00100010 2
455 8 01000100 4
456 9 01000100 4
457 10 10001000 8
458 11 10001000 8
459 12 01000100 4
460 13 01000100 4
461 14 10001000 8
462 15 10001000 8
463
464 Inversion value calculation:
465
466 2 colour formula: 1 << (colour * 2)
467 4 colour formula: 1 << colour
468 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
469
470 For example, where logical colour 0 has been mapped to a physical colour in
471 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
472 the inversion operation. (The lower three bits of the physical colour would be
473 used to set the underlying colour information affected by the inversion
474 operation.)
475
476 An operation in the interrupt code would then combine the bitmaps for all
477 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
478 combined for groups of logical colours as follows:
479
480 Logical colours
481 ---------------
482 0, 2, 8, 10
483 4, 6, 12, 14
484 5, 7, 13, 15
485 1, 3, 9, 11
486
487 These combined bitmaps would be EORed with the existing palette register
488 values in order to perform the value inversion necessary to produce the
489 flashing effect.
490
491 Thus, in the VDU 19 operation, the appropriate inversion value would be
492 calculated for the logical colour, and this value would then be combined with
493 other inversion values in a dedicated memory location corresponding to the
494 colour's group as indicated above. Meanwhile, the palette channel values would
495 be derived from the lower three bits of the specified physical colour and
496 combined with other palette data in dedicated memory locations corresponding
497 to the palette registers.
498
499 Interestingly, although flashing colours on the BBC Micro are controlled by
500 toggling bit 0 of the &FE20 control register location for the Video ULA, the
501 actual colour inversion is done in hardware.
502
503 Enhancement: Palette Definition Lists
504 -------------------------------------
505
506 It can be useful to redefine the palette in order to change the colours
507 available for a particular region of the screen, particularly in modes where
508 the choice of colours is constrained, and if an increased colour depth were
509 available, palette redefinition would be useful to give the illusion of more
510 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
511 by using interrupt-driven timers, but a more efficient approach would involve
512 presenting lists of palette definitions to the ULA so that it can change the
513 palette at a particular display line.
514
515 One might define a palette redefinition list in a region of memory and then
516 communicate its contents to the ULA by writing the address and length of the
517 list, along with the display line at which the palette is to be changed, to
518 ULA registers such that the ULA buffers the list and performs the redefinition
519 at the appropriate time. Throughput/bandwidth considerations might impose
520 restrictions on the practical length of such a list, however.
521
522 Enhancement: Palette-Free Modes
523 -------------------------------
524
525 Palette-free modes might be defined where bit values directly correspond to
526 the red, green and blue channels, although this would mostly make sense only
527 for modes with depths greater than the standard 4 bits per pixel, and such
528 modes would require more memory than MODE 2 if they were to have an acceptable
529 resolution.
530
531 Enhancement: Display Suspend
532 ----------------------------
533
534 Especially when writing to the screen memory, it could be beneficial to be
535 able to suspend the ULA's access to the memory, instead producing blank values
536 for all screen pixels until a program is ready to reveal the screen. This is
537 different from palette blanking since with a blank palette, the ULA is still
538 reading screen memory and translating its contents into pixel values that end
539 up being blank.
540
541 This function is reminiscent of a capability of the ZX81, albeit necessary on
542 that hardware to reduce the load on the system CPU which was responsible for
543 producing the video output. By allowing display suspend on the Electron, the
544 performance benefit would be derived from giving the CPU full access to the
545 memory bandwidth.
546
547 The region blanking feature mentioned above could be implemented using this
548 enhancement instead of employing palette blanking for the affected lines of
549 the display.
550
551 Enhancement: Memory Filling
552 ---------------------------
553
554 A capability that could be given to an enhanced ULA is that of permitting the
555 ULA to write to screen memory as well being able to read from it. Although
556 such a capability would probably not be useful in conjunction with the
557 existing read operations when producing a screen display, and insufficient
558 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
559 capability could be offered during a display suspend period (as described
560 above), permitting a more efficient mechanism to rapidly fill memory with a
561 predetermined value.
562
563 This capability could also support block filling, where the limits of the
564 filled memory would be defined by the position and size of a screen area,
565 although this would demand the provision of additional registers in the ULA to
566 retain the details of such areas and additional logic to control the fill
567 operation.
568
569 Enhancement: Region Filling
570 ---------------------------
571
572 An alternative to memory writing might involve indicating regions using
573 additional registers or memory where the ULA fills regions of the screen with
574 content instead of reading from memory. Unlike hardware sprites which should
575 realistically provide varied content, region filling could employ single
576 colours or patterns, and one advantage of doing so would be that the ULA need
577 not access memory at all within a particular region.
578
579 Regions would be defined on a row-by-row basis. Instead of reading memory and
580 blitting a direct representation to the screen, the ULA would read region
581 definitions containing a start column, region width and colour details. There
582 might be a certain number of definitions allowed per row, or the ULA might
583 just traverse an ordered list of such definitions with each one indicating the
584 row, start column, region width and colour details.
585
586 One could even compress this information further by requiring only the row,
587 start column and colour details with each subsequent definition terminating
588 the effect of the previous one. However, one would also need to consider the
589 convenience of preparing such definitions and whether efficient access to
590 definitions for a particular row might be desirable. It might also be
591 desirable to avoid having to prepare definitions for "empty" areas of the
592 screen, effectively making the definition of the screen contents employ
593 run-length encoding and employ only colour plus length information.
594
595 One application of region filling is that of simple 2D and 3D shape rendering.
596 Although it is entirely possible to plot such shapes to the screen and have
597 the ULA blit the memory contents to the screen, such operations consume
598 bandwidth both in the initial plotting and in the final transfer to the
599 screen. Region filling would reduce such bandwidth usage substantially.
600
601 This way of representing screen images would make certain kinds of images
602 unfeasible to represent - consider alternating single pixel values which could
603 easily occur in some character bitmaps - even if an internal queue of regions
604 were to be supported such that the ULA could read ahead and buffer such
605 "bandwidth intensive" areas. Thus, the ULA might be better served providing
606 this feature for certain areas of the display only as some kind of special
607 graphics window.
608
609 Enhancement: Hardware Sprites
610 -----------------------------
611
612 An enhanced ULA might provide hardware sprites, but this would be done in an
613 way that is incompatible with the standard ULA, since no &FE*X locations are
614 available for allocation. To keep the facility simple, hardware sprites would
615 have a standard byte width and height.
616
617 The specification of sprites could involve the reservation of 16 locations
618 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
619 location pair referring to the sprite data. By limiting the ULA to dealing
620 with a fixed number of sprites, the work required inside the ULA would be
621 reduced since it would avoid having to deal with arbitrary numbers of sprites.
622
623 The principal limitation on providing hardware sprites is that of having to
624 obtain sprite data, given that the ULA is usually required to retrieve screen
625 data, and given the lack of memory bandwidth available to retrieve sprite data
626 (particularly from multiple sprites supposedly at the same position) and
627 screen data simultaneously. Although the ULA could potentially read sprite
628 data and screen data in alternate memory accesses in screen modes where the
629 bandwidth is not already fully utilised, this would result in a degradation of
630 performance.
631
632 Enhancement: Additional Screen Mode Configurations
633 --------------------------------------------------
634
635 Alternative screen mode configurations could be supported. The ULA has to
636 produce 640 pixel values across the screen, with pixel doubling or quadrupling
637 employed to fill the screen width:
638
639 Screen width Columns Scaling Depth Bytes
640 ------------ ------- ------- ----- -----
641 640 80 x1 1 80
642 320 40 x2 1, 2 40, 80
643 160 20 x4 2, 4 40, 80
644
645 It must also use at most 80 byte-sized memory accesses to provide the
646 information for the display. Given that characters must occupy an 8x8 pixel
647 array, if a configuration featuring anything other than 20, 40 or 80 character
648 columns is to be supported, compromises must be made such as the introduction
649 of blank pixels either between characters (such as occurs between rows in MODE
650 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
651 in MODE 3 and 6). Consider the following configuration:
652
653 Screen width Columns Scaling Depth Bytes Blank
654 ------------ ------- ------- ----- ------ -----
655 208 26 x3 1, 2 26, 52 16
656
657 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
658 colours could be provided, with 16 blank pixel values (out of a total of 640)
659 generated either at the start or end (or split between the start and end) of
660 each scanline.
661
662 Enhancement: Character Attributes
663 ---------------------------------
664
665 The BBC Micro MODE 7 employs something resembling character attributes to
666 support teletext displays, but depends on circuitry providing a character
667 generator. The ZX Spectrum, on the other hand, provides character attributes
668 as a means of colouring bitmapped graphics. Although such a feature is very
669 limiting as the sole means of providing multicolour graphics, in situations
670 where the choice is between low resolution multicolour graphics or high
671 resolution monochrome graphics, character attributes provide a potentially
672 useful compromise.
673
674 For each byte read, the ULA must deliver 8 pixel values (out of a total of
675 640) to the video output, doing so by either emptying its pixel buffer on a
676 pixel per cycle basis, or by multiplying pixels and thus holding them for more
677 than one cycle. For example for a screen mode having 640 pixels in width:
678
679 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
680 Reads: B B
681 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
682
683 And for a screen mode having 320 pixels in width:
684
685 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
686 Reads: B
687 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
688
689 However, in modes where less than 80 bytes are required to generate the pixel
690 values, an enhanced ULA might be able to read additional bytes between those
691 providing the bitmapped graphics data:
692
693 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
694 Reads: B A
695 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
696
697 These additional bytes could provide colour information for the bitmapped data
698 in the following character column (of 8 pixels). Since it would be desirable
699 to apply attribute data to the first column, the initial 8 cycles might be
700 configured to not produce pixel values.
701
702 For an entire character, attribute data need only be read for the first row of
703 pixels for a character. The subsequent rows would have attribute information
704 applied to them, although this would require the attribute data to be stored
705 in some kind of buffer. Thus, the following access pattern would be observed:
706
707 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
708
709 A whole byte used for colour information for a whole character would result in
710 a choice of 256 colours, and this might be somewhat excessive. By only reading
711 attribute bytes at every other opportunity, a choice of 16 colours could be
712 applied individually to two characters.
713
714 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
715 Reads: B A B -
716 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
717
718 Further reductions in attribute data access, offering 4 colours for every
719 character in a four character block, for example, might also be worth
720 considering.
721
722 Consider the following configurations for screen modes with a colour depth of
723 1 bit per pixel for bitmap information:
724
725 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
726 ------------ ------- ------- --------- --------- ------- ------------
727 320 40 x2 40 40 256 &5300
728 320 40 x2 40 20 16 &5580 -> &5500
729 320 40 x2 40 10 4 &56C0 -> &5600
730 208 26 x3 26 26 256 &62C0 -> &6200
731 208 26 x3 26 13 16 &6460 -> &6400
732
733 Enhancement: MODE 7 Emulation using Character Attributes
734 --------------------------------------------------------
735
736 If the scheme of applying attributes to character regions were employed to
737 emulate MODE 7, in conjunction with the MODE 6 display technique, the
738 following configuration would be required:
739
740 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
741 ------------ ------- ---- --------- --------- ------- ------------
742 320 40 25 40 20 16 &5ECC -> &5E00
743 320 40 25 40 10 4 &5FC6 -> &5F00
744
745 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
746 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
747 at least make a limited 40-column multicolour mode available as a substitute
748 for MODE 7.
749
750 Enhancement: High Resolution Graphics and Mode Layouts
751 ------------------------------------------------------
752
753 Screen modes with different screen memory mappings, higher resolutions and
754 larger colour depths might be possible, but this would in most cases involve
755 the allocation of more screen memory, and the ULA would probably then be
756 obliged to page in such memory for the CPU to be able to sensibly access it
757 all. Merely changing the memory mappings in order to have Archimedes-style
758 row-oriented screen addresses (instead of character-oriented addresses) could
759 be done for the existing modes, but this might not be sufficiently beneficial,
760 especially since accessing regions of the screen would involve incrementing
761 pointers by amounts that are inconvenient on an 8-bit CPU.
762
763 Enhancement: Genlock Support
764 ----------------------------
765
766 The ULA generates a video signal in conjunction with circuitry producing the
767 output features necessary for the correct display of the screen image.
768 However, it appears that the ULA drives the video synchronisation mechanism
769 instead of reacting to an existing signal. Genlock support might be possible
770 if the ULA were made to be responsive to such external signals, resetting its
771 address generators upon receiving synchronisation events.
772
773 Enhancement: Improved Sound
774 ---------------------------
775
776 The standard ULA reserves &FE*6 for sound generation and cassette input/output
777 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
778 cassette I/O), thus making it impossible to support multiple channels within
779 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
780 and an enhanced ULA could adopt this interface.
781
782 The BBC Micro uses the SN76489 chip to produce sound, and the entire
783 functionality of this chip could be emulated for enhanced sound, with a subset
784 of the functionality exposed via the &FE*6 interface.
785
786 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
787
788 Enhancement: Waveform Upload
789 ----------------------------
790
791 As with a hardware sprite function, waveforms could be uploaded or referenced
792 using locations as registers referencing memory regions.
793
794 Enhancement: Sound Input/Output
795 -------------------------------
796
797 Since the ULA already controls audio input/output for cassette-based data, it
798 would have been interesting to entertain the idea of sampling and output of
799 sounds through the cassette interface. However, a significant amount of
800 circuitry is employed to process the input signal for use by the ULA and to
801 process the output signal for recording.
802
803 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
804
805 Enhancement: BBC ULA Compatibility
806 ----------------------------------
807
808 Although some new ULA functions could be defined in a way that is also
809 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
810 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
811 map, but controls various functions specific to the 6845 video controller;
812 &FE08-F is reserved for the serial controller. It therefore becomes possible
813 to disregard compatibility where compatibility is already disregarded for a
814 particular area of functionality.
815
816 &FE20-F maps to video ULA functionality on the BBC Micro which provides
817 control over the palette (using address &FE21, compared to &FE07-F on the
818 Electron) and other system-specific functions. Since the location usage is
819 generally incompatible, this region could be reused for other purposes.
820
821 Enhancement: Increased RAM, ULA and CPU Performance
822 ---------------------------------------------------
823
824 More modern implementations of the hardware might feature faster RAM coupled
825 with an increased ULA clock frequency in order to increase the bandwidth
826 available to the ULA and to the CPU in situations where the ULA is not needed
827 to perform work. A ULA employing a 32MHz clock would be able to complete the
828 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
829 to access the RAM for the following 250ns even in display modes requiring the
830 retrieval of a byte for the display every 500ns. The CPU could, subject to
831 timing issues, run at 2MHz even in MODE 0, 1 and 2.
832
833 A scheme such as that described above would have a similar effect to the
834 scheme employed in the BBC Micro, although the latter made use of RAM with a
835 wider bandwidth in order to complete memory transfers within 250ns and thus
836 permit the CPU to run continuously at 2MHz.
837
838 Higher bandwidth could potentially be used to implement exotic features such
839 as RAM-resident hardware sprites or indeed any feature demanding RAM access
840 concurrent with the production of the display image.
841
842 Enhancement: Multiple CPU Stacks
843 --------------------------------
844
845 The 6502 maintains a stack for subroutine calls and register storage in page
846 &01. Although the stack register can be manipulated using the TSX and TXS
847 instructions, thereby permitting the maintenance of multiple stack regions and
848 thus the potential coexistence of multiple programs each using a separate
849 region, only programs that make little use of the stack (perhaps avoiding
850 deeply-nested subroutine invocations and significant register storage) would
851 be able to coexist without overwriting each other's stacks.
852
853 One way that this issue could be alleviated would involve the provision of a
854 facility to redirect accesses to page &01 to other areas of memory. The ULA
855 would provide a register that defines a physical page for the use of the CPU's
856 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
857 change the asserted address lines to redirect the access to the appropriate
858 physical region.
859
860 By providing an 8-bit register, mapping to the most significant byte (MSB) of
861 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
862 register value before the access is made. Where multiple programs coexist,
863 upon switching programs, the register would be updated to point the ULA to the
864 appropriate stack location, thus providing a simple memory management unit
865 (MMU) capability.
866
867 ULA Pin Functions
868 -----------------
869
870 The functions of the ULA pins are described in the Electron Service Manual. Of
871 interest to video processing are the following:
872
873 CSYNC (low during horizontal or vertical synchronisation periods, high
874 otherwise)
875
876 HS (low during horizontal synchronisation periods, high otherwise)
877
878 RED, GREEN, BLUE (pixel colour outputs)
879
880 CLOCK IN (a 16MHz clock input, 4V peak to peak)
881
882 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
883
884 More general memory access pins:
885
886 RAM0...RAM3 (data lines to/from the RAM)
887
888 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
889
890 RAS (row address strobe setting the row address on a negative edge - see the
891 timing notes)
892
893 CAS (column address strobe setting the column address on a negative edge -
894 see the timing notes)
895
896 WE (sets write enable with logic 0, read with logic 1)
897
898 ROM (select data access from ROM)
899
900 CPU-oriented memory access pins:
901
902 A0...A15 (CPU address lines)
903
904 PD0...PD7 (CPU data lines)
905
906 R/W (indicates CPU write with logic 0, CPU read with logic 1)
907
908 Interrupt-related pins:
909
910 NMI (CPU request for uninterrupted 1MHz access to memory)
911
912 IRQ (signal event to CPU)
913
914 POR (power-on reset, resetting the ULA on a positive edge and asserting the
915 CPU's RST pin)
916
917 RST (master reset for the CPU signalled on power-up and by the Break key)
918
919 Keyboard-related pins:
920
921 KBD0...KBD3 (keyboard inputs)
922
923 CAPS LOCK (control status LED)
924
925 Sound-related pins:
926
927 SOUND O/P (sound output using internal oscillator)
928
929 Cassette-related pins:
930
931 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
932
933 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
934
935 CAS RC (detect high tone)
936
937 CAS MO (motor relay output)
938
939 ÷13 IN (~1200 baud clock input)
940
941 ULA Socket
942 ----------
943
944 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
945
946 References
947 ----------
948
949 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
950
951 About this Document
952 -------------------
953
954 The most recent version of this document and accompanying distribution should
955 be available from the following location:
956
957 http://hgweb.boddie.org.uk/ULA
958
959 Copyright and licence information can be found in the docs directory of this
960 distribution - see docs/COPYING.txt for more information.