1 The Acorn Electron ULA
2 ======================
3
4 Principal Design and Feature Constraints
5 ----------------------------------------
6
7 The features of the ULA are limited in sophistication by the amount of time
8 and resources that can be allocated to each activity supporting the
9 fundamental features and obligations of the unit. Maintaining a screen display
10 based on the contents of RAM itself requires the ULA to have exclusive access
11 to various hardware resources for a significant period of time.
12
13 Whilst other elements of the ULA can in principle run in parallel with the
14 display refresh activity, they cannot also access the RAM at the same time.
15 Consequently, other features that might use the RAM must accept a reduced
16 allocation of that resource in comparison to a hypothetical architecture where
17 concurrent RAM access is possible at all times.
18
19 Thus, the principal constraint for many features is bandwidth. The duration of
20 access to hardware resources is one aspect of this; the rate at which such
21 resources can be accessed is another. For example, the RAM is not fast enough
22 to support access more frequently than one byte per 2MHz cycle, and for screen
23 modes involving 80 bytes of screen data per scanline, there are no free cycles
24 for anything other than the production of pixel output during the active
25 scanline periods.
26
27 Another constraint is imposed by the method of RAM access provided by the ULA.
28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing
29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to
30 provide display data for the most demanding screen modes. However, this
31 mechanism's timing requirements are beyond the capabilities of the CPU when
32 running at 2MHz.
33
34 Consequently, the CPU will only ever be able to access RAM via the ULA at
35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
36 refresh the display, the ULA is still able to make use of the idle part of
37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
39 cycle), thus supporting the less demanding screen modes.
40
41 Timing
42 ------
43
44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256
45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles
46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /
47 312 ~= 128 cycles). This is consistent with the observation that each scanline
48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
49 out of 64 microseconds in each scanline.
50
51 (In fact, since the ULA is seeking to provide an image for an interlaced
52 625-line display, there are in fact two "fields" involved, one providing 312
53 scanlines and one providing 313 scanlines. See below for a description of the
54 video system.)
55
56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
57 each providing two bits of each byte) using two cycles within the 500ns period
58 of the 2MHz clock to complete each access operation. Since the CPU and ULA
59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
60 effectively run at 1MHz (since every other 500ns period involves the ULA
61 accessing RAM) during transfers of screen data.
62
63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided
64 by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is
65 approximately 62.5ns. To access the memory, the following patterns
66 corresponding to 16MHz cycles are required:
67
68 Time (ns): 0-------------- 500------------- ...
69 2 MHz cycle: 0 1 ...
70 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
71 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...
72 ~RAS: /---\___________/---\___________ ...
73 ~CAS: /-----\___/-\___/-----\___/-\___ ...
74 Address events: A B C A B C ...
75 Data events: F S F S ...
76
77 ~RAS ops: 1 0 1 0 ...
78 ~CAS ops: 1 0 1 0 1 0 1 0 ...
79
80 Address ops: a b c a b c ...
81 Data ops: s f s f ...
82
83 ~WE: ......W ...
84 PHI OUT: \_______________/--------------- ...
85 CPU (RAM): L D ...
86 RnW: R ...
87
88 PHI OUT: \_______/-------\_______/------- ...
89 CPU (ROM): L D L D ...
90 RnW: R R ...
91
92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.
93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.
94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.
95
96 Here, "A" and "B" respectively indicate the row and first column addresses
97 being latched into the RAM (on a negative edge for ~RAS and ~CAS
98 respectively), and "C" indicates the second column address being latched into
99 the RAM. Presumably, the first and second half-bytes can be read at "F" and
100 "S" respectively, and the row and column addresses must be made available at
101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and
102 "s" for the first and second half-bytes respectively.
103
104 For the CPU, "L" indicates the point at which an address is taken from the CPU
105 address bus, on a negative edge of PHI OUT, with "D" being the point at which
106 data may either be read or be asserted for writing, on a positive edge of PHI
107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low
108 for writing or high for reading, and thus propagates RnW from the CPU, this
109 would need to be done before data would be retrieved and, according to the
110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS
111 brought low.
112
113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column
114 address access time of 90ns (maximum), which appears to mean that ~RAS must be
115 held low for at least 150ns and that ~CAS must be held low for at least 90ns
116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44
117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"
118 is 1.5 cycles.
119
120 Note that the Service Manual refers to the negative edge of RAS and CAS, but
121 the datasheet for the similar TM4164EC4 product shows latching on the negative
122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
124 "page mode" provides the appropriate behaviour for that particular product.
125
126 The CPU, when accessing the RAM alone, apparently does not make use of the
127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in
128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
129 accessing ROM (and potentially sideways RAM). The principal limitation is the
130 amount of time needed between issuing an address and receiving an entire byte
131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the
132 4 cycles that would be required for 2MHz operation.
133
134 See: Acorn Electron Advanced User Guide
135 See: Acorn Electron Service Manual
136 http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
139 See: One of the Most Popular 65,536-Bit (64K) Dynamic RAMs The TMS 4164
140 http://smithsonianchips.si.edu/augarten/p64.htm
141
142 A Note on 8-Bit Wide RAM Access
143 -------------------------------
144
145 It is worth considering the timing when 8 bits of data can be obtained at once
146 from the RAM chips:
147
148 Time (ns): 0-------------- 500------------- ...
149 2 MHz cycle: 0 1 ...
150 8 MHz cycle: 0 1 2 3 0 1 2 3 ...
151 /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_ ...
152 ~RAS: /---\___________/---\___________ ...
153 ~CAS: /-------\_______/-------\_______ ...
154 Address events: A B A B ...
155 Data events: E E ...
156
157 ~RAS ops: 1 0 1 0 ...
158 ~CAS ops: 1 0 1 0 ...
159
160 Address ops: a b a b ...
161 Data ops: f s f ...
162
163 ~WE: ........W ...
164 PHI OUT: \_______/-------\_______/------- ...
165 CPU: L D L D ...
166 RnW: R R ...
167
168 Here, "E" indicates the availability of an entire byte.
169
170 Since only one fetch is required per 2MHz cycle, instead of two fetches for
171 the 4-bit wide RAM arrangement, it seems likely that longer 8MHz cycles could
172 be used to coordinate the necessary signalling.
173
174 Another conceivable simplification from using an 8-bit wide RAM access channel
175 with a single access within each 2MHz cycle is the possibility of allowing the
176 CPU to signal directly to the RAM instead of having the ULA perform the access
177 signalling on the CPU's behalf.
178
179 CPU Clock Notes
180 ---------------
181
182 "The 6502 receives an external square-wave clock input signal on pin 37, which
183 is usually labeled PHI0. [...] This clock input is processed within the 6502
184 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
185 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
186 through two inverters and a push-pull amplifier. The same network of
187 transistors within the 6502 which generates PHI2 is also tied to PHI1, and
188 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
189 available to external devices is so that they know when they can access the
190 CPU. When PHI1 is high, this means that external devices can read from the
191 address bus or data bus; when PHI2 is high, this means that external devices
192 can write to the data bus."
193
194 See: http://lateblt.livejournal.com/88105.html
195
196 "The 6502 has a synchronous memory bus where the master clock is divided into
197 two phases (Phase 1 and Phase 2). The address is always generated during Phase
198 1 and all memory accesses take place during Phase 2."
199
200 See: http://www.jmargolin.com/vgens/vgens.htm
201
202 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
203 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
204 when PHI1 is high.
205
206 Bandwidth Figures
207 -----------------
208
209 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
210 total lines, with 80 cycles occurring in the active periods of display
211 scanlines, the following bandwidth calculations can be performed:
212
213 Total theoretical maximum:
214 128 cycles * 312 lines
215 = 39936 bytes
216
217 MODE 0, 1, 2:
218 ULA: 80 cycles * 256 lines
219 = 20480 bytes
220 CPU: 48 cycles / 2 * 256 lines
221 + 128 cycles / 2 * (312 - 256) lines
222 = 9728 bytes
223
224 MODE 3:
225 ULA: 80 cycles * 24 rows * 8 lines
226 = 15360 bytes
227 CPU: 48 cycles / 2 * 24 rows * 8 lines
228 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
229 = 12288 bytes
230
231 MODE 4, 5:
232 ULA: 40 cycles * 256 lines
233 = 10240 bytes
234 CPU: (40 cycles + 48 cycles / 2) * 256 lines
235 + 128 cycles / 2 * (312 - 256) lines
236 = 19968 bytes
237
238 MODE 6:
239 ULA: 40 cycles * 24 rows * 8 lines
240 = 7680 bytes
241 CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
242 + 128 cycles / 2 * (312 - (24 rows * 8 lines))
243 = 19968 bytes
244
245 Here, the division of 2 for CPU accesses is performed to indicate that the CPU
246 only uses every other access opportunity even in uncontended periods. See the
247 2MHz RAM Access enhancement below for bandwidth calculations that consider
248 this limitation removed.
249
250 Video Timing
251 ------------
252
253 According to 8.7 in the Service Manual, and the PAL Wikipedia page,
254 approximately 4.7µs is used for the sync pulse, 5.7µs for the "back porch"
255 (including the "colour burst"), and 1.65µs for the "front porch", totalling
256 12.05µs and thus leaving 51.95µs for the active video signal for each
257 scanline. As the Service Manual suggests in the oscilloscope traces, the
258 display information is transmitted more or less centred within the active
259 video period since the ULA will only be providing pixel data for 40µs in each
260 scanline.
261
262 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
263 each scanline can be divided into 1024 cycles, although only 640 at most are
264 actively used to provide pixel data. Pixel data production should only occur
265 within a certain period on each scanline, approximately 262 cycles after the
266 start of hsync:
267
268 active video period = 51.95µs
269 pixel data period = 40µs
270 total silent period = 51.95µs - 40µs = 11.95µs
271 silent periods (before and after) = 11.95µs / 2 = 5.975µs
272 hsync and back porch period = 4.7µs + 5.7µs = 10.4µs
273 time before pixel data period = 10.4µs + 5.975µs = 16.375µs
274 pixel data period start cycle = 16.375µs / 62.5ns = 262
275
276 By choosing a number divisible by 8, the RAM access mechanism can be
277 synchronised with the pixel production. Thus, 256 is a more appropriate start
278 cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync
279 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"
280 document) occurs at cycle 0.
281
282 To summarise:
283
284 HS signal starts at cycle 0 on each horizontal scanline
285 HS signal ends approximately 4µs later at cycle 64
286 Pixel data starts approximately 12µs later at cycle 256
287
288 "Re: Electron Memory Contention" provides measurements that appear consistent
289 with these calculations.
290
291 The "vertical blanking period", meaning the period before picture information
292 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of
293 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5
294 lines. Thus, the first visible scanline on the first field of a frame occurs
295 half way through the 23rd scanline period measured from the start of vsync
296 (indicated by "V" in the diagrams below):
297
298 10 20 23
299 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8
300 Line from 1: 0 22 3
301 Line on screen: .:::::VVVVV::::: 12233445566
302 |_________________________________________________|
303 25 line vertical blanking period
304
305 In the second field of a frame, the first visible scanline coincides with the
306 24th scanline period measured from the start of line 313 in the frame:
307
308 310 336
309 Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
310 Line from 313: 0 23 4
311 Line on screen: 88:::::VVVVV:::: 11223344
312 288 | |
313 |_________________________________________________|
314 25 line vertical blanking period
315
316 In order to consider only full lines, we might consider the start of each
317 frame to occur 23 lines after the start of vsync.
318
319 Again, it is likely that pixel data production should only occur on scanlines
320 within a certain period on each frame. The "625/50" document indicates that
321 only a certain region is "safe" to use, suggesting a vertically centred region
322 with approximately 15 blank lines above and below the picture. However, the
323 "PAL TV timing and voltages" document suggests 28 blank lines above and below
324 the picture. This would centre the 256 lines within the 312 lines of each
325 field and thus provide a start of picture approximately 5.5 or 5 lines after
326 the end of the blanking period or 28 or 27.5 lines after the start of vsync.
327
328 To summarise:
329
330 CSYNC signal starts at cycle 0
331 CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560
332 Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672
333
334 See: http://en.wikipedia.org/wiki/PAL
335 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal
336 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes
337 http://lipas.uwasa.fi/~f76998/video/modes/
338 See: PAL TV timing and voltages
339 http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/
340 See: Line Standards
341 http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html
342 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards
343 http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf
344 See: Re: Electron Memory Contention
345 http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109
346
347 RAM Integrated Circuits
348 -----------------------
349
350 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series
351 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are
352 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,
353 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,
354 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.
355
356 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and
357 the Samsung-produced KM41464 series is apparently equivalent to the Texas
358 Instruments 4164 chips presumably used in the Electron.
359
360 The TM4164EC4 series combines 4 64K x 1b units into a single package and
361 appears similar to the TM4164EA4 featured on the Electron's circuit diagram
362 (in the Advanced User Guide but not the Service Manual), and it also has 22
363 pins providing 3 additional inputs and 3 additional outputs over the 16 pins
364 of the individual 4164-15 modules, presumably allowing concurrent access to
365 the packaged memory units.
366
367 As far as currently available replacements are concerned, the NTE4164 is a
368 potential candidate: according to the Vetco Electronics entry, it is
369 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar
370 parts include the NTE2164 and the NTE6664, both of which appear to have
371 largely the same performance and connection characteristics. Meanwhile, the
372 NTE21256 appears to be a 16-pin replacement with four times the capacity that
373 maintains the single data input and output pins. Using the NTE21256 as a
374 replacement for all ICs combined would be difficult because of the single bit
375 output.
376
377 Another device equivalent to the 4164-15 appears to be available under the
378 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web
379 site lists data sheets for other devices on the same page, but these are
380 different and actually appear to be provided under the 41574 product code (but
381 are listed under 41464-10) and appear to be replacements for the TM4164EC4:
382 the Samsung KM41464A-15 and NEC µPD41464 employ 18 pins, eliminating 4 pins by
383 employing 4 pins for both input and output.
384
385 Pins I/O pins Row access Column access
386 ---- -------- ---------- -------------
387 TM4164EC4 22 4 + 4 150ns (15) 90ns (15)
388 KM41464AP 18 4 150ns (15) 75ns (15)
389 NTE21256 16 1 + 1 150ns 75ns
390 HYB 4164-2 16 1 + 1 150ns 100ns
391 µPD41464 18 4 120ns (12) 60ns (12)
392
393 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module
394 http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
395 See: Dynamic RAMS
396 http://www.unicornelectronics.com/IC/DYNAMIC.html
397 See: New old stock 8x 4164 chips
398 http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock
399 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode
400 http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf
401 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory
402 http://www.vetco.net/catalog/product_info.php?products_id=2806
403 See: NTE4164 - IC-NMOS 64K DRAM 150NS
404 http://www.vetco.net/catalog/product_info.php?products_id=3680
405 See: NTE21256 - IC-256K DRAM 150NS
406 http://www.vetco.net/catalog/product_info.php?products_id=2799
407 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
408 http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf
409 See: NTE6664 - IC-MOS 64K DRAM 150NS
410 http://www.vetco.net/catalog/product_info.php?products_id=5213
411 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM
412 http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf
413 See: 4164-150: MAJOR BRANDS
414 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1
415 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)
416 http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf
417 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode
418 http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf
419 See: NEC µ41464 65,536 x 4-Bit Dynamic NMOS RAM
420 http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf
421 See: 41464-10: MAJOR BRANDS
422 http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1
423
424 Interrupts
425 ----------
426
427 The ULA generates IRQs (maskable interrupts) according to certain conditions
428 and these conditions are controlled by location &FE00:
429
430 * Vertical sync (bottom of displayed screen)
431 * 50MHz real time clock
432 * Transmit data empty
433 * Receive data full
434 * High tone detect
435
436 The ULA is also used to clear interrupt conditions through location &FE05. Of
437 particular significance is bit 7, which must be set if an NMI (non-maskable
438 interrupt) has occurred and has thus suspended ULA access to memory, restoring
439 the normal function of the ULA.
440
441 ROM Paging
442 ----------
443
444 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
445 mappings exist:
446
447 8 keyboard
448 9 keyboard (duplicate)
449 10 BASIC ROM
450 11 BASIC ROM (duplicate)
451
452 Paging in a ROM involves the following procedure:
453
454 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
455 2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
456 selected.
457 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
458 whilst writing the desired ROM number n in bits 0 to 2.
459
460 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686
461
462 Keyboard Access
463 ---------------
464
465 The keyboard pages appear to be accessed at 1MHz just like the RAM.
466
467 See: https://stardot.org.uk/forums/viewtopic.php?p=254155#p254155
468
469 Shadow/Expanded Memory
470 ----------------------
471
472 The Electron exposes all sixteen address lines and all eight data lines
473 through the expansion bus. Using such lines, it is possible to provide
474 additional memory - typically sideways ROM and RAM - on expansion cards and
475 through cartridges, although the official cartridge specification provides
476 fewer address lines and only seeks to provide access to memory in 16K units.
477
478 Various modifications and upgrades were developed to offer "turbo"
479 capabilities to the Electron, permitting the CPU to access a separate 8K of
480 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
481 the ULA through additional logic. However, an enhanced ULA might support
482 independent CPU access to memory over the expansion bus by allowing itself to
483 be discharged from providing access to memory, potentially for a range of
484 addresses, and for the CPU to communicate with external memory uninterrupted.
485
486 Sideways RAM/ROM and Upper Memory Access
487 ----------------------------------------
488
489 Although the ULA controls the CPU clock, effectively slowing or stopping the
490 CPU when the ULA needs to access screen memory, it is apparently able to allow
491 the CPU to access addresses of &8000 and above - the upper region of memory -
492 at 2MHz independently of any access to RAM that the ULA might be performing,
493 only blocking the CPU if it attempts to access addresses of &7FFF and below
494 during any ULA memory access - the lower region of memory - by stopping or
495 stalling its clock.
496
497 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the
498 CPU clock if the line goes low, when the CPU is attempting to access the lower
499 region of memory.
500
501 Hardware Scrolling (and Enhancement)
502 ------------------------------------
503
504 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
505 the least significant 5 bits being zero, thus limiting the scrolling
506 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
507 using the same layout of these addresses.
508
509 |--&FE02--------------| |--&FE03--------------|
510 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
511
512 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
513
514 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
515 memory to pixel locations is character oriented. A change in 8 bytes would
516 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
517 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
518 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
519 Guide).
520
521 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
522 of changing the screen address by 2 bytes is the change in the number of lines
523 from the initial and final character rows that need reading by the ULA, which
524 would need to maintain this state information (although this is a relatively
525 trivial change). Another pitfall is the complication that might be introduced
526 to software writing bitmaps of character height to the screen.
527
528 See: http://pastraiser.com/computers/acornelectron/acornelectron.html
529
530 Enhancement: Mode Layouts
531 -------------------------
532
533 Merely changing the screen memory mappings in order to have Archimedes-style
534 row-oriented screen addresses (instead of character-oriented addresses) could
535 be done for the existing modes, but this might not be sufficiently beneficial,
536 especially since accessing regions of the screen would involve incrementing
537 pointers by amounts that are inconvenient on an 8-bit CPU.
538
539 However, instead of using a Archimedes-style mapping, column-oriented screen
540 addresses could be more feasibly employed: incrementing the address would
541 reference the vertical screen location below the currently-referenced location
542 (just as occurs within characters using the existing ULA); instead of
543 returning to the top of the character row and referencing the next horizontal
544 location after eight bytes, the address would reference the next character row
545 and continue to reference locations downwards over the height of the screen
546 until reaching the bottom; at the bottom, the next location would be the next
547 horizontal location at the top of the screen.
548
549 In other words, the memory layout for the screen would resemble the following
550 (for MODE 2):
551
552 &3000 &3100 ... &7F00
553 &3001 &3101
554 ... ...
555 &3007
556 &3008
557 ...
558 ... ...
559 &30FF ... &7FFF
560
561 Since there are 256 pixel rows, each column of locations would be addressable
562 using the low byte of the address. Meanwhile, the high byte would be
563 incremented to address different columns. Thus, addressing screen locations
564 would become a lot more convenient and potentially much more efficient for
565 certain kinds of graphical output.
566
567 One potential complication with this simplified addressing scheme arises with
568 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported
569 with the existing ULA) would be achieved by incrementing or decrementing the
570 screen start address; by one character row, it would involve adding or
571 subtracting 8. However, the ULA only supports multiples of 64 when changing the
572 screen start address. Thus, if such a scheme were to be adopted, three
573 additional bits would need to be supported in the screen start register (see
574 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal
575 scrolling would be much improved even under the severe constraints of the
576 existing ULA: only adjustments of 256 to the screen start address would be
577 required to produce single-location scrolling of as few as two pixels in MODE 2
578 (four pixels in MODEs 1 and 5, eight pixels otherwise).
579
580 More disruptive is the effect of this alternative layout on software.
581 Presumably, compatibility with the BBC Micro was the primary goal of the
582 Electron's hardware design. With the character-oriented screen layout in
583 place, system software (and application software accessing the screen
584 directly) would be relying on this layout to run on the Electron with little
585 or no modification. Although it might have been possible to change the system
586 software to use this column-oriented layout instead, this would have incurred
587 a development cost and caused additional work porting things like games to the
588 Electron. Moreover, a separate branch of the software from that supporting the
589 BBC Micro and closer derivatives would then have needed maintaining.
590
591 The decision to use the character-oriented layout in the BBC Micro may have
592 been related to the choice of circuitry and to facilitate a convenient
593 hardware implementation, and by the time the Electron was planned, it was too
594 late to do anything about this somewhat unfortunate choice.
595
596 Pixel Layouts
597 -------------
598
599 The pixel layouts are as follows:
600
601 Modes Depth (bpp) Pixels (from bits)
602 ----- ----------- ------------------
603 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
604 1, 5 2 73 62 51 40
605 2 4 7531 6420
606
607 Since the ULA reads a half-byte at a time, one might expect it to attempt to
608 produce pixels for every half-byte, as opposed to handling entire bytes.
609 However, the pixel layout is not conducive to producing pixels as soon as a
610 half-byte has been read for a given full-byte location: in 1bpp modes the
611 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel
612 data is spread across the entire byte in different ways.
613
614 An alternative arrangement might be as follows:
615
616 Modes Depth (bpp) Pixels (from bits)
617 ----- ----------- ------------------
618 0, 3, 4, 6 1 7 6 5 4 3 2 1 0
619 1, 5 2 76 54 32 10
620 2 4 7654 3210
621
622 Just as the mode layouts were presumably decided by compatibility with the BBC
623 Micro, the pixel layouts will have been maintained for similar reasons.
624 Unfortunately, this layout prevents any optimisation of the ULA for handling
625 half-byte pixel data generally.
626
627 Enhancement: The Missing MODE 4
628 -------------------------------
629
630 The Electron inherits its screen mode selection from the BBC Micro, where MODE
631 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.
632 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,
633 however, and they are merely implemented by skipping two scanlines in every
634 ten after the eight required to produce a character line. Thus, such modes
635 provide a 24-row display.
636
637 In principle, nothing prevents this "text mode" effect being applied to other
638 modes. The 20-column modes are not well-suited to displaying text, which
639 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than
640 2. Although the need for a non-monochrome 40-column text mode is addressed by
641 MODE 7 on the BBC Micro, the Electron lacks such a mode.
642
643 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it
644 would occupy MODE 4 instead of the current MODE 4:
645
646 Screen mode Size (kilobytes) Colours Rows Resolution
647 ----------- ---------------- ------- ---- ----------
648 0 20 2 32 640x256
649 1 20 4 32 320x256
650 2 20 16 32 160x256
651 3 16 2 24 640x256
652 4 (new) 16 4 24 320x256
653 4 (old) 10 2 32 320x256
654 5 10 4 32 160x256
655 6 8 2 24 320x256
656
657 Thus, for increasing mode numbers, the size of each mode would be the same or
658 less than the preceding mode.
659
660 Enhancement: 2MHz RAM Access
661 ----------------------------
662
663 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
664 when not competing with the ULA only accesses RAM every other 2MHz cycle (as
665 if the ULA still needed to access the RAM), one useful enhancement would be a
666 mechanism to let the CPU take over the ULA cycles outside the ULA's period of
667 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
668 3.
669
670 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
671
672 Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
673 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
674
675 In MODE 4 to 6:
676
677 Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
678 On a non-display line: CCCCCCCC (instead of C_C_C_C_)
679
680 This would improve CPU bandwidth as follows:
681
682 Standard ULA Enhanced ULA % Total Bandwidth Speedup
683 MODE 0, 1, 2 9728 bytes 19456 bytes 24% -> 49% 2
684 MODE 3 12288 bytes 24576 bytes 31% -> 62% 2
685 MODE 4, 5 19968 bytes 29696 bytes 50% -> 74% 1.5
686 MODE 6 19968 bytes 32256 bytes 50% -> 81% 1.6
687
688 (Here, the uncontended total 2MHz bandwidth for a display period would be
689 39936 bytes, being 128 cycles per line over 312 lines.)
690
691 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
692 because all access opportunities to RAM are doubled. Meanwhile, in the other
693 modes, some CPU accesses occur alongside ULA accesses and thus cannot be
694 doubled, but the CPU bandwidth increase is still significant.
695
696 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
697 within the time constraints of 2MHz operation. There is no time remaining in a
698 2MHz cycle for the CPU to receive and process any retrieved data once the
699 necessary signalling has been performed. The only way for the CPU to be able
700 to access the RAM quickly enough would be to do away with the double 4-bit
701 access mechanism and to have a single 8-bit channel to the memory. This would
702 require twice as many 1-bit RAM chips or a different kind of RAM chip, but it
703 would also potentially simplify the ULA.
704
705 Enhancement: Region Blanking
706 ----------------------------
707
708 The problem of permitting character-oriented blitting in programs whilst
709 scrolling the screen by sub-character amounts could be mitigated by permitting
710 a region of the display to be blank, such as the final lines of the display.
711 Consider the following vertical scrolling by 2 bytes that would cause an
712 initial character row of 6 lines and a final character row of 2 lines:
713
714 6 lines - initial, partial character row
715 248 lines - 31 complete rows
716 2 lines - final, partial character row
717
718 If a routine were in use that wrote 8 line bitmaps to the partial character
719 row now split in two, it would be advisable to hide one of the regions in
720 order to prevent content appearing in the wrong place on screen (such as
721 content meant to appear at the top "leaking" onto the bottom). Blanking 6
722 lines would be sufficient, as can be seen from the following cases.
723
724 Scrolling up by 2 lines:
725
726 6 lines - initial, partial character row
727 240 lines - 30 complete rows
728 4 lines - part of 1 complete row
729 -----------------------------------------------------------------
730 4 lines - part of 1 complete row (hidden to maintain 250 lines)
731 2 lines - final, partial character row (hidden)
732
733 Scrolling down by 2 lines:
734
735 2 lines - initial, partial character row
736 248 lines - 31 complete rows
737 ----------------------------------------------------------
738 6 lines - final, partial character row (hidden)
739
740 Thus, in this case, region blanking would impose a 250 line display with the
741 bottom 6 lines blank.
742
743 See the description of the display suspend enhancement for a more efficient
744 way of blanking lines than merely blanking the palette whilst allowing the CPU
745 to perform useful work during the blanking period.
746
747 To control the blanking or suspending of lines at the top and bottom of the
748 display, a memory location could be dedicated to the task: the upper 4 bits
749 could define a blanking region of up to 16 lines at the top of the screen,
750 whereas the lower 4 bits could define such a region at the bottom of the
751 screen. If more lines were required, two locations could be employed, allowing
752 the top and bottom regions to occupy the entire screen.
753
754 Enhancement: Screen Height Adjustment
755 -------------------------------------
756
757 The height of the screen could be configurable in order to reduce screen
758 memory consumption. This is not quite done in MODE 3 and 6 since the start of
759 the screen appears to be rounded down to the nearest page, but by reducing the
760 height by amounts more than a page, savings would be possible. For example:
761
762 Screen width Depth Height Bytes per line Saving in bytes Start address
763 ------------ ----- ------ -------------- --------------- -------------
764 640 1 252 80 320 &3140 -> &3100
765 640 1 248 80 640 &3280 -> &3200
766 320 1 240 40 640 &5A80 -> &5A00
767 320 2 240 80 1280 &3500
768
769 Screen Mode Selection
770 ---------------------
771
772 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider
773 range of modes, the other bits of &FE*7 (related to sound, cassette
774 input/output and the Caps Lock LED) would need to be reassigned and bit 0
775 potentially being made available for use.
776
777 Enhancement: Palette Definition
778 -------------------------------
779
780 Since all memory accesses go via the ULA, an enhanced ULA could employ more
781 specific addresses than &FE*X to perform enhanced functions. For example, the
782 palette control is done using &FE*8-F and merely involves selecting predefined
783 colours, whereas an enhanced ULA could support the redefinition of all 16
784 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
785 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
786 specifications similar to those used on the Archimedes.
787
788 The principal limitation here is actually the hardware: the Electron has only
789 a single output line for each of the red, green and blue channels, and if
790 those outputs are strictly digital and can only be set to a "high" and "low"
791 value, then only the existing eight colours are possible. If a modern ULA were
792 able to output analogue values (or values at well-defined points between the
793 high and low values, such as the half-on value supported by the Amstrad CPC
794 series), it would still need to be assessed whether the circuitry could
795 successfully handle and propagate such values. Various sources indicate that
796 only "TTL levels" are supported by the RGB output circuit, and since there are
797 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it
798 is likely that the ULA is expected to provide only "high" or "low" values.
799
800 Short of adding extra outputs from the ULA (either additional red, green and
801 blue outputs or a combined intensity output), another approach might involve
802 some kind of modulation where an output value might be encoded in multiple
803 pulses at a higher frequency than the pixel frequency. However, this would
804 demand additional circuitry outside the ULA, and component RGB monitors would
805 probably not be able to take advantage of this feature; only UHF and composite
806 video devices (the latter with the composite video colour support enabled on
807 the Electron's circuit board) would potentially benefit.
808
809 Flashing Colours
810 ----------------
811
812 According to the Advanced User Guide, "The cursor and flashing colours are
813 entirely generated in software: This means that all of the logical to physical
814 colour map must be changed to cause colours to flash." This appears to suggest
815 that the palette registers must be updated upon the flash counter - read and
816 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the
817 colour pairs to be any combination of colours might be possible, instead of
818 having colour complements as pairs.
819
820 It is conceivable that the interrupt code responsible does the simple thing
821 and merely inverts the current values for any logical colours (LC) for which
822 the associated physical colour (as supplied as the second parameter to the VDU
823 19 call) has the top bit of its four bit value set. These top bits are not
824 recorded in the palette registers but are presumably recorded separately and
825 used to build bitmaps as follows:
826
827 LC 2 colour 4 colour 16 colour 4-bit value for inversion
828 -- -------- -------- --------- -------------------------
829 0 00010001 00010001 00010001 1, 1, 1
830 1 01000100 00100010 00010001 4, 2, 1
831 2 01000100 00100010 4, 2
832 3 10001000 00100010 8, 2
833 4 00010001 1
834 5 00010001 1
835 6 00100010 2
836 7 00100010 2
837 8 01000100 4
838 9 01000100 4
839 10 10001000 8
840 11 10001000 8
841 12 01000100 4
842 13 01000100 4
843 14 10001000 8
844 15 10001000 8
845
846 Inversion value calculation:
847
848 2 colour formula: 1 << (colour * 2)
849 4 colour formula: 1 << colour
850 16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))
851
852 For example, where logical colour 0 has been mapped to a physical colour in
853 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to
854 the inversion operation. (The lower three bits of the physical colour would be
855 used to set the underlying colour information affected by the inversion
856 operation.)
857
858 An operation in the interrupt code would then combine the bitmaps for all
859 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being
860 combined for groups of logical colours as follows:
861
862 Logical colours
863 ---------------
864 0, 2, 8, 10
865 4, 6, 12, 14
866 5, 7, 13, 15
867 1, 3, 9, 11
868
869 These combined bitmaps would be EORed with the existing palette register
870 values in order to perform the value inversion necessary to produce the
871 flashing effect.
872
873 Thus, in the VDU 19 operation, the appropriate inversion value would be
874 calculated for the logical colour, and this value would then be combined with
875 other inversion values in a dedicated memory location corresponding to the
876 colour's group as indicated above. Meanwhile, the palette channel values would
877 be derived from the lower three bits of the specified physical colour and
878 combined with other palette data in dedicated memory locations corresponding
879 to the palette registers.
880
881 Interestingly, although flashing colours on the BBC Micro are controlled by
882 toggling bit 0 of the &FE20 control register location for the Video ULA, the
883 actual colour inversion is done in hardware.
884
885 Enhancement: Palette Definition Lists
886 -------------------------------------
887
888 It can be useful to redefine the palette in order to change the colours
889 available for a particular region of the screen, particularly in modes where
890 the choice of colours is constrained, and if an increased colour depth were
891 available, palette redefinition would be useful to give the illusion of more
892 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
893 by using interrupt-driven timers, but a more efficient approach would involve
894 presenting lists of palette definitions to the ULA so that it can change the
895 palette at a particular display line.
896
897 One might define a palette redefinition list in a region of memory and then
898 communicate its contents to the ULA by writing the address and length of the
899 list, along with the display line at which the palette is to be changed, to
900 ULA registers such that the ULA buffers the list and performs the redefinition
901 at the appropriate time. Throughput/bandwidth considerations might impose
902 restrictions on the practical length of such a list, however.
903
904 Enhancement: Display Synchronisation Interrupts
905 -----------------------------------------------
906
907 When completing each scanline of the display, the ULA could trigger an
908 interrupt. Since this might impact system performance substantially, the
909 feature would probably need to be configurable, and it might be sufficient to
910 have an interrupt only after a certain number of display lines instead.
911 Permitting the CPU to take action after eight lines would allow palette
912 switching and other effects to occur on a character row basis.
913
914 The ULA provides an interrupt at the end of the display period, presumably so
915 that software can schedule updates to the screen, avoid flickering or tearing,
916 and so on. However, some applications might benefit from an interrupt at, or
917 just before, the start of the display period so that palette modifications or
918 similar effects could be scheduled.
919
920 Enhancement: Palette-Free Modes
921 -------------------------------
922
923 Palette-free modes might be defined where bit values directly correspond to
924 the red, green and blue channels, although this would mostly make sense only
925 for modes with depths greater than the standard 4 bits per pixel, and such
926 modes would require more memory than MODE 2 if they were to have an acceptable
927 resolution.
928
929 Enhancement: Display Suspend
930 ----------------------------
931
932 Especially when writing to the screen memory, it could be beneficial to be
933 able to suspend the ULA's access to the memory, instead producing blank values
934 for all screen pixels until a program is ready to reveal the screen. This is
935 different from palette blanking since with a blank palette, the ULA is still
936 reading screen memory and translating its contents into pixel values that end
937 up being blank.
938
939 This function is reminiscent of a capability of the ZX81, albeit necessary on
940 that hardware to reduce the load on the system CPU which was responsible for
941 producing the video output. By allowing display suspend on the Electron, the
942 performance benefit would be derived from giving the CPU full access to the
943 memory bandwidth.
944
945 The region blanking feature mentioned above could be implemented using this
946 enhancement instead of employing palette blanking for the affected lines of
947 the display.
948
949 Enhancement: Memory Filling
950 ---------------------------
951
952 A capability that could be given to an enhanced ULA is that of permitting the
953 ULA to write to screen memory as well being able to read from it. Although
954 such a capability would probably not be useful in conjunction with the
955 existing read operations when producing a screen display, and insufficient
956 bandwidth would exist to do so in high-bandwidth screen modes anyway, the
957 capability could be offered during a display suspend period (as described
958 above), permitting a more efficient mechanism to rapidly fill memory with a
959 predetermined value.
960
961 This capability could also support block filling, where the limits of the
962 filled memory would be defined by the position and size of a screen area,
963 although this would demand the provision of additional registers in the ULA to
964 retain the details of such areas and additional logic to control the fill
965 operation.
966
967 Enhancement: Region Filling
968 ---------------------------
969
970 An alternative to memory writing might involve indicating regions using
971 additional registers or memory where the ULA fills regions of the screen with
972 content instead of reading from memory. Unlike hardware sprites which should
973 realistically provide varied content, region filling could employ single
974 colours or patterns, and one advantage of doing so would be that the ULA need
975 not access memory at all within a particular region.
976
977 Regions would be defined on a row-by-row basis. Instead of reading memory and
978 blitting a direct representation to the screen, the ULA would read region
979 definitions containing a start column, region width and colour details. There
980 might be a certain number of definitions allowed per row, or the ULA might
981 just traverse an ordered list of such definitions with each one indicating the
982 row, start column, region width and colour details.
983
984 One could even compress this information further by requiring only the row,
985 start column and colour details with each subsequent definition terminating
986 the effect of the previous one. However, one would also need to consider the
987 convenience of preparing such definitions and whether efficient access to
988 definitions for a particular row might be desirable. It might also be
989 desirable to avoid having to prepare definitions for "empty" areas of the
990 screen, effectively making the definition of the screen contents employ
991 run-length encoding and employ only colour plus length information.
992
993 One application of region filling is that of simple 2D and 3D shape rendering.
994 Although it is entirely possible to plot such shapes to the screen and have
995 the ULA blit the memory contents to the screen, such operations consume
996 bandwidth both in the initial plotting and in the final transfer to the
997 screen. Region filling would reduce such bandwidth usage substantially.
998
999 This way of representing screen images would make certain kinds of images
1000 unfeasible to represent - consider alternating single pixel values which could
1001 easily occur in some character bitmaps - even if an internal queue of regions
1002 were to be supported such that the ULA could read ahead and buffer such
1003 "bandwidth intensive" areas. Thus, the ULA might be better served providing
1004 this feature for certain areas of the display only as some kind of special
1005 graphics window.
1006
1007 Enhancement: Hardware Sprites
1008 -----------------------------
1009
1010 An enhanced ULA might provide hardware sprites, but this would be done in an
1011 way that is incompatible with the standard ULA, since no &FE*X locations are
1012 available for allocation. To keep the facility simple, hardware sprites would
1013 have a standard byte width and height.
1014
1015 The specification of sprites could involve the reservation of 16 locations
1016 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
1017 location pair referring to the sprite data. By limiting the ULA to dealing
1018 with a fixed number of sprites, the work required inside the ULA would be
1019 reduced since it would avoid having to deal with arbitrary numbers of sprites.
1020
1021 The principal limitation on providing hardware sprites is that of having to
1022 obtain sprite data, given that the ULA is usually required to retrieve screen
1023 data, and given the lack of memory bandwidth available to retrieve sprite data
1024 (particularly from multiple sprites supposedly at the same position) and
1025 screen data simultaneously. Although the ULA could potentially read sprite
1026 data and screen data in alternate memory accesses in screen modes where the
1027 bandwidth is not already fully utilised, this would result in a degradation of
1028 performance.
1029
1030 Enhancement: Additional Screen Mode Configurations
1031 --------------------------------------------------
1032
1033 Alternative screen mode configurations could be supported. The ULA has to
1034 produce 640 pixel values across the screen, with pixel doubling or quadrupling
1035 employed to fill the screen width:
1036
1037 Screen width Columns Scaling Depth Bytes
1038 ------------ ------- ------- ----- -----
1039 640 80 x1 1 80
1040 320 40 x2 1, 2 40, 80
1041 160 20 x4 2, 4 40, 80
1042
1043 It must also use at most 80 byte-sized memory accesses to provide the
1044 information for the display. Given that characters must occupy an 8x8 pixel
1045 array, if a configuration featuring anything other than 20, 40 or 80 character
1046 columns is to be supported, compromises must be made such as the introduction
1047 of blank pixels either between characters (such as occurs between rows in MODE
1048 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
1049 in MODE 3 and 6). Consider the following configuration:
1050
1051 Screen width Columns Scaling Depth Bytes Blank
1052 ------------ ------- ------- ----- ------ -----
1053 208 26 x3 1, 2 26, 52 16
1054
1055 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
1056 colours could be provided, with 16 blank pixel values (out of a total of 640)
1057 generated either at the start or end (or split between the start and end) of
1058 each scanline.
1059
1060 Enhancement: Character Attributes
1061 ---------------------------------
1062
1063 The BBC Micro MODE 7 employs something resembling character attributes to
1064 support teletext displays, but depends on circuitry providing a character
1065 generator. The ZX Spectrum, on the other hand, provides character attributes
1066 as a means of colouring bitmapped graphics. Although such a feature is very
1067 limiting as the sole means of providing multicolour graphics, in situations
1068 where the choice is between low resolution multicolour graphics or high
1069 resolution monochrome graphics, character attributes provide a potentially
1070 useful compromise.
1071
1072 For each byte read, the ULA must deliver 8 pixel values (out of a total of
1073 640) to the video output, doing so by either emptying its pixel buffer on a
1074 pixel per cycle basis, or by multiplying pixels and thus holding them for more
1075 than one cycle. For example for a screen mode having 640 pixels in width:
1076
1077 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1078 Reads: B B
1079 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1080
1081 And for a screen mode having 320 pixels in width:
1082
1083 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1084 Reads: B
1085 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1086
1087 However, in modes where less than 80 bytes are required to generate the pixel
1088 values, an enhanced ULA might be able to read additional bytes between those
1089 providing the bitmapped graphics data:
1090
1091 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1092 Reads: B A
1093 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1094
1095 These additional bytes could provide colour information for the bitmapped data
1096 in the following character column (of 8 pixels). Since it would be desirable
1097 to apply attribute data to the first column, the initial 8 cycles might be
1098 configured to not produce pixel values.
1099
1100 For an entire character, attribute data need only be read for the first row of
1101 pixels for a character. The subsequent rows would have attribute information
1102 applied to them, although this would require the attribute data to be stored
1103 in some kind of buffer. Thus, the following access pattern would be observed:
1104
1105 Reads: A B _ B _ B _ B _ B _ B _ B _ B ...
1106
1107 In modes 3 and 6, the blank display lines could be used to retrieve attribute
1108 data:
1109
1110 Reads (blank): A _ A _ A _ A _ A _ A _ A _ A _ ...
1111 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1112 Reads (active): B _ B _ B _ B _ B _ B _ B _ B _ ...
1113 ...
1114
1115 See below for a discussion of using this for character data as well.
1116
1117 A whole byte used for colour information for a whole character would result in
1118 a choice of 256 colours, and this might be somewhat excessive. By only reading
1119 attribute bytes at every other opportunity, a choice of 16 colours could be
1120 applied individually to two characters.
1121
1122 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
1123 Reads: B A B -
1124 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
1125
1126 Further reductions in attribute data access, offering 4 colours for every
1127 character in a four character block, for example, might also be worth
1128 considering.
1129
1130 Consider the following configurations for screen modes with a colour depth of
1131 1 bit per pixel for bitmap information:
1132
1133 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
1134 ------------ ------- ------- --------- --------- ------- ------------
1135 320 40 x2 40 40 256 &5300
1136 320 40 x2 40 20 16 &5580 -> &5500
1137 320 40 x2 40 10 4 &56C0 -> &5600
1138 208 26 x3 26 26 256 &62C0 -> &6200
1139 208 26 x3 26 13 16 &6460 -> &6400
1140
1141 Enhancement: Text-Only Modes using Character and Attribute Data
1142 ---------------------------------------------------------------
1143
1144 In modes 3 and 6, the blank display lines could be used to retrieve character
1145 and attribute data instead of trying to insert it between bitmap data accesses,
1146 but this data would then need to be retained:
1147
1148 Reads: A C A C A C A C A C A C A C A C ...
1149 Reads: B _ B _ B _ B _ B _ B _ B _ B _ ...
1150
1151 Only attribute (A) and character (C) reads would require screen memory
1152 storage. Bitmap data reads (B) would involve either accesses to memory to
1153 obtain character definition details or could, at the cost of special storage
1154 in the ULA, involve accesses within the ULA that would then free up the RAM.
1155 However, the CPU would not benefit from having any extra access slots due to
1156 the limitations of the RAM access mechanism.
1157
1158 A scheme without caching might be possible. The same line of memory addresses
1159 might be visited over and over again for eight display lines, with an index
1160 into the bitmap data being incremented from zero to seven. The access patterns
1161 would look like this:
1162
1163 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 0)
1164 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 1)
1165 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 2)
1166 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 3)
1167 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 4)
1168 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 5)
1169 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 6)
1170 Reads: C B C B C B C B C B C B C B C B ... (generate data from index 7)
1171
1172 The bandwidth requirements would be the sum of the accesses to read the
1173 character values (repeatedly) and those to read the bitmap data to reproduce
1174 the characters on screen.
1175
1176 Enhancement: MODE 7 Emulation using Character Attributes
1177 --------------------------------------------------------
1178
1179 If the scheme of applying attributes to character regions were employed to
1180 emulate MODE 7, in conjunction with the MODE 6 display technique, the
1181 following configuration would be required:
1182
1183 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
1184 ------------ ------- ---- --------- --------- ------- ------------
1185 320 40 25 40 20 16 &5ECC -> &5E00
1186 320 40 25 40 10 4 &5FC6 -> &5F00
1187
1188 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
1189 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
1190 at least make a limited 40-column multicolour mode available as a substitute
1191 for MODE 7.
1192
1193 Using the text-only enhancement with caching of data or with repeated reads of
1194 the same character data line for eight display lines, the storage requirements
1195 would be diminished substantially:
1196
1197 Screen width Columns Rows Bytes (C) Bytes (A) Colours Screen start
1198 ------------ ------- ---- --------- --------- ------- ------------
1199 320 40 25 40 20 16 &7A94 -> &7A00
1200 320 40 25 40 10 4 &7B1E -> &7B00
1201 320 40 25 40 5 2 &7B9B -> &7B00
1202 320 40 25 40 0 (2) &7C18 -> &7C00
1203 640 80 25 80 40 16 &7448 -> &7400
1204 640 80 25 80 20 4 &763C -> &7600
1205 640 80 25 80 10 2 &7736 -> &7700
1206 640 80 25 80 0 (2) &7830 -> &7800
1207
1208 Note that the colours describe the locally defined attributes for each
1209 character. When no attribute information is provided, the colours are defined
1210 globally.
1211
1212 Enhancement: Compressed Character Data
1213 --------------------------------------
1214
1215 Another observation about text-only modes is that they only need to store a
1216 restricted set of bitmapped data values. Encoding this set of values in a
1217 smaller unit of storage than a byte could possibly help to reduce the amount
1218 of storage and bandwidth required to reproduce the characters on the display.
1219
1220 Enhancement: High Resolution Graphics
1221 -------------------------------------
1222
1223 Screen modes with higher resolutions and larger colour depths might be
1224 possible, but this would in most cases involve the allocation of more screen
1225 memory, and the ULA would probably then be obliged to page in such memory for
1226 the CPU to be able to sensibly access it all.
1227
1228 Enhancement: Genlock Support
1229 ----------------------------
1230
1231 The ULA generates a video signal in conjunction with circuitry producing the
1232 output features necessary for the correct display of the screen image.
1233 However, it appears that the ULA drives the video synchronisation mechanism
1234 instead of reacting to an existing signal. Genlock support might be possible
1235 if the ULA were made to be responsive to such external signals, resetting its
1236 address generators upon receiving synchronisation events.
1237
1238 Enhancement: Improved Sound
1239 ---------------------------
1240
1241 The standard ULA reserves &FE*6 for sound generation and cassette input/output
1242 (with bits 1 and 2 of &FE*7 being used to select either sound generation or
1243 cassette I/O), thus making it impossible to support multiple channels within
1244 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
1245 and an enhanced ULA could adopt this interface.
1246
1247 The BBC Micro uses the SN76489 chip to produce sound, and the entire
1248 functionality of this chip could be emulated for enhanced sound, with a subset
1249 of the functionality exposed via the &FE*6 interface.
1250
1251 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
1252 See: http://www.smspower.org/Development/SN76489
1253
1254 Enhancement: Waveform Upload
1255 ----------------------------
1256
1257 As with a hardware sprite function, waveforms could be uploaded or referenced
1258 using locations as registers referencing memory regions.
1259
1260 Enhancement: Sound Input/Output
1261 -------------------------------
1262
1263 Since the ULA already controls audio input/output for cassette-based data, it
1264 would have been interesting to entertain the idea of sampling and output of
1265 sounds through the cassette interface. However, a significant amount of
1266 circuitry is employed to process the input signal for use by the ULA and to
1267 process the output signal for recording.
1268
1269 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11
1270
1271 Enhancement: BBC ULA Compatibility
1272 ----------------------------------
1273
1274 Although some new ULA functions could be defined in a way that is also
1275 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
1276 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
1277 map, but controls various functions specific to the 6845 video controller;
1278 &FE08-F is reserved for the serial controller. It therefore becomes possible
1279 to disregard compatibility where compatibility is already disregarded for a
1280 particular area of functionality.
1281
1282 &FE20-F maps to video ULA functionality on the BBC Micro which provides
1283 control over the palette (using address &FE21, compared to &FE07-F on the
1284 Electron) and other system-specific functions. Since the location usage is
1285 generally incompatible, this region could be reused for other purposes.
1286
1287 Enhancement: Increased RAM, ULA and CPU Performance
1288 ---------------------------------------------------
1289
1290 More modern implementations of the hardware might feature faster RAM coupled
1291 with an increased ULA clock frequency in order to increase the bandwidth
1292 available to the ULA and to the CPU in situations where the ULA is not needed
1293 to perform work. A ULA employing a 32MHz clock would be able to complete the
1294 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU
1295 to access the RAM for the following 250ns even in display modes requiring the
1296 retrieval of a byte for the display every 500ns. The CPU could, subject to
1297 timing issues, run at 2MHz even in MODE 0, 1 and 2.
1298
1299 A scheme such as that described above would have a similar effect to the
1300 scheme employed in the BBC Micro, although the latter made use of RAM with a
1301 wider bandwidth in order to complete memory transfers within 250ns and thus
1302 permit the CPU to run continuously at 2MHz.
1303
1304 Higher bandwidth could potentially be used to implement exotic features such
1305 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1306 concurrent with the production of the display image.
1307
1308 Enhancement: Multiple CPU Stacks and Zero Pages
1309 -----------------------------------------------
1310
1311 The 6502 maintains a stack for subroutine calls and register storage in page
1312 &01. Although the stack register can be manipulated using the TSX and TXS
1313 instructions, thereby permitting the maintenance of multiple stack regions and
1314 thus the potential coexistence of multiple programs each using a separate
1315 region, only programs that make little use of the stack (perhaps avoiding
1316 deeply-nested subroutine invocations and significant register storage) would
1317 be able to coexist without overwriting each other's stacks.
1318
1319 One way that this issue could be alleviated would involve the provision of a
1320 facility to redirect accesses to page &01 to other areas of memory. The ULA
1321 would provide a register that defines a physical page for the use of the CPU's
1322 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1323 change the asserted address lines to redirect the access to the appropriate
1324 physical region.
1325
1326 By providing an 8-bit register, mapping to the most significant byte (MSB) of
1327 a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1328 register value before the access is made. Where multiple programs coexist,
1329 upon switching programs, the register would be updated to point the ULA to the
1330 appropriate stack location, thus providing a simple memory management unit
1331 (MMU) capability.
1332
1333 In a similar fashion, zero page accesses could also be redirected so that code
1334 could run from sideways RAM and have zero page operations redirected to "upper
1335 memory" - for example, to page &BE (with stack accesses redirected to page
1336 &BF, perhaps) - thereby permitting most CPU operations to occur without
1337 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the
1338 CPU as it contends with the ULA for memory access.
1339
1340 Such facilities could also be provided by a separate circuit between the CPU
1341 and ULA in a fashion similar to that employed by a "turbo" board, but unlike
1342 such boards, no additional RAM would be provided: all memory accesses would
1343 occur as normal through the ULA, albeit redirected when configured
1344 appropriately.
1345
1346 ULA Pin Functions
1347 -----------------
1348
1349 The functions of the ULA pins are described in the Electron Service Manual. Of
1350 interest to video processing are the following:
1351
1352 CSYNC (low during horizontal or vertical synchronisation periods, high
1353 otherwise)
1354
1355 HS (low during horizontal synchronisation periods, high otherwise)
1356
1357 RED, GREEN, BLUE (pixel colour outputs)
1358
1359 CLOCK IN (a 16MHz clock input, 4V peak to peak)
1360
1361 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
1362
1363 More general memory access pins:
1364
1365 RAM0...RAM3 (data lines to/from the RAM)
1366
1367 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
1368
1369 RAS (row address strobe setting the row address on a negative edge - see the
1370 timing notes)
1371
1372 CAS (column address strobe setting the column address on a negative edge -
1373 see the timing notes)
1374
1375 WE (sets write enable with logic 0, read with logic 1)
1376
1377 ROM (select data access from ROM)
1378
1379 CPU-oriented memory access pins:
1380
1381 A0...A15 (CPU address lines)
1382
1383 PD0...PD7 (CPU data lines)
1384
1385 R/W (indicates CPU write with logic 0, CPU read with logic 1)
1386
1387 Interrupt-related pins:
1388
1389 NMI (CPU request for uninterrupted 1MHz access to memory)
1390
1391 IRQ (signal event to CPU)
1392
1393 POR (power-on reset, resetting the ULA on a positive edge and asserting the
1394 CPU's RST pin)
1395
1396 RST (master reset for the CPU signalled on power-up and by the Break key)
1397
1398 Keyboard-related pins:
1399
1400 KBD0...KBD3 (keyboard inputs)
1401
1402 CAPS LOCK (control status LED)
1403
1404 Sound-related pins:
1405
1406 SOUND O/P (sound output using internal oscillator)
1407
1408 Cassette-related pins:
1409
1410 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
1411
1412 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
1413
1414 CAS RC (detect high tone)
1415
1416 CAS MO (motor relay output)
1417
1418 ÷13 IN (~1200 baud clock input)
1419
1420 ULA Socket
1421 ----------
1422
1423 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.
1424
1425 References
1426 ----------
1427
1428 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm
1429
1430 About this Document
1431 -------------------
1432
1433 The most recent version of this document and accompanying distribution should
1434 be available from the following location:
1435
1436 http://hgweb.boddie.org.uk/ULA
1437
1438 Copyright and licence information can be found in the docs directory of this
1439 distribution - see docs/COPYING.txt for more information.