1 Timing
2 ------
3
4 According to the above (15.3.2 in the AUG), there are 312 scanlines, 256 of
5 which are used to generate pixel data. At 50Hz, this means that 128 cycles are
6 spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles / 312
7 ~= 128 cycles). This is consistent with the observation that each scanline
8 requires at most 80 bytes of data, and that the ULA is apparently busy for 40
9 out of 64 microseconds in each scanline.
10
11 See: Acorn Electron Advanced User Guide
12 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
13
14 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,
15 each providing two bits of each byte) using two cycles within the 500ns period
16 of the 2MHz clock to complete each access operation. Since the CPU and ULA
17 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must
18 effectively run at 1MHz (since every other 500ns period involves the ULA
19 accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz
20 frequency is divided by the ULA (IC1) depending on the screen mode in use.
21
22 See: Acorn Electron Service Manual
23 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
24
25 Each 16MHz cycle is approximately 62.5ns. To access the memory, the following
26 patterns corresponding to 16MHz cycles are required:
27
28 Time (ns): 0-------------- 500------------ ...
29 2 MHz cycle: 0 1 ...
30 16 MHz cycle: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ...
31 ~RAS: 0 1 0 1 ...
32 ~CAS: 0 1 0 1 0 1 0 1 ...
33 A B B A B B ...
34 F S F S ...
35 a b b a b b ...
36
37 Here, "A" indicates the row and column addresses being latched into the RAM
38 (on a negative edge for ~RAS and ~CAS respectively), and "B" indicates the
39 second column address being latched into the RAM. Presumably, the first and
40 second half-bytes can be read at "F" and "S" respectively, and the row and
41 column addresses must be made available at "a" and "b" respectively at the
42 latest.
43
44 Note that the Service Manual refers to the negative edge of RAS and CAS, but
45 the datasheet for the similar TM4164EC4 product shows latching on the negative
46 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to
47 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
48 "page mode" provides the appropriate behaviour for that particular product.
49
50 See: http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf
51
52 Each 62.5ns cycle happens to correspond to 64µs divided by 1024, meaning that
53 each scanline can be divided into 1024 cycles, although only 640 at most are
54 actively used to provide pixel data.
55
56 Shadow/Expanded Memory
57 ----------------------
58
59 The Electron exposes all sixteen address lines and all eight data lines
60 through the expansion bus. Using such lines, it is possible to provide
61 additional memory - typically sideways ROM and RAM - on expansion cards and
62 through cartridges, although the official cartridge specification provides
63 fewer address lines and only seeks to provide access to memory in 16K units.
64
65 Various modifications and upgrades were developed to offer "turbo"
66 capabilities to the Electron, permitting the CPU to access a separate 8K of
67 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via
68 the ULA through additional logic. However, an enhanced ULA might support
69 independent CPU access to memory over the expansion bus by allowing itself to
70 be discharged from providing access to memory, potentially for a range of
71 addresses, and for the CPU to communicate with external memory uninterrupted.
72
73 Hardware Scrolling
74 ------------------
75
76 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with
77 the least significant 5 bits being zero, thus limiting the scrolling
78 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes
79 using the same layout of these addresses.
80
81 |--&FE02--------------| |--&FE03--------------|
82 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX
83
84 XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX
85
86 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen
87 memory to pixel locations is character oriented. A change in 8 bytes would
88 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in
89 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually
90 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User
91 Guide).
92
93 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall
94 of changing the screen address by 2 bytes is the change in the number of lines
95 from the initial and final character rows that need reading by the ULA, which
96 would need to maintain this state information (although this is a relatively
97 trivial change). Another pitfall is the complication that might be introduced
98 to software writing bitmaps of character height to the screen.
99
100 Region Blanking
101 ---------------
102
103 The problem of permitting character-oriented blitting in programs whilst
104 scrolling the screen by sub-character amounts could be mitigated by permitting
105 a region of the display to be blank, such as the final lines of the display.
106 Consider the following vertical scrolling by 2 bytes that would cause an
107 initial character row of 6 lines and a final character row of 2 lines:
108
109 6 lines - initial, partial character row
110 248 lines - 31 complete rows
111 2 lines - final, partial character row
112
113 If a routine were in use that wrote 8 line bitmaps to the partial character
114 row now split in two, it would be advisable to hide one of the regions in
115 order to prevent content appearing in the wrong place on screen (such as
116 content meant to appear at the top "leaking" onto the bottom). Blanking 6
117 lines would be sufficient, as can be seen from the following cases.
118
119 Scrolling up by 2 lines:
120
121 6 lines - initial, partial character row
122 240 lines - 30 complete rows
123 4 lines - part of 1 complete row
124 -----------------------------------------------------------------
125 4 lines - part of 1 complete row (hidden to maintain 250 lines)
126 2 lines - final, partial character row (hidden)
127
128 Scrolling down by 2 lines:
129
130 2 lines - initial, partial character row
131 248 lines - 31 complete rows
132 ----------------------------------------------------------
133 6 lines - final, partial character row (hidden)
134
135 Thus, in this case, region blanking would impose a 250 line display with the
136 bottom 6 lines blank.
137
138 Screen Height Adjustment
139 ------------------------
140
141 The height of the screen could be configurable in order to reduce screen
142 memory consumption. This is not quite done in MODE 3 and 6 since the start of
143 the screen appears to be rounded down to the nearest page, but by reducing the
144 height by amounts more than a page, savings would be possible. For example:
145
146 Screen width Depth Height Bytes per line Saving in bytes Start address
147 ------------ ----- ------ -------------- --------------- -------------
148 640 1 252 80 320 &3140 -> &3100
149 640 1 248 80 640 &3280 -> &3200
150 320 1 240 40 640 &5A80 -> &5A00
151 320 2 240 80 1280 &3500
152
153 Palette Definition
154 ------------------
155
156 Since all memory accesses go via the ULA, an enhanced ULA could employ more
157 specific addresses than &FE*X to perform enhanced functions. For example, the
158 palette control is done using &FE*8-F and merely involves selecting predefined
159 colours, whereas an enhanced ULA could support the redefinition of all 16
160 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F
161 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour
162 specifications similar to those used on the Archimedes.
163
164 The principal limitation here is actually the hardware: the Electron has only
165 a single output line for each of the red, green and blue channels, and if
166 those outputs are strictly digital and can only be set to a "high" and "low"
167 value, then only the existing eight colours are possible. If a modern ULA were
168 able to output analogue values, it would still need to be assessed whether the
169 circuitry could successfully handle and propagate such values.
170
171 Palette Definition Lists
172 ------------------------
173
174 It can be useful to redefine the palette in order to change the colours
175 available for a particular region of the screen, particularly in modes where
176 the choice of colours is constrained, and if an increased colour depth were
177 available, palette redefinition would be useful to give the illusion of more
178 than 16 colours in MODE 2. Traditionally, palette redefinition has been done
179 by using interrupt-driven timers, but a more efficient approach would involve
180 presenting lists of palette definitions to the ULA so that it can change the
181 palette at a particular display line.
182
183 One might define a palette redefinition list in a region of memory and then
184 communicate its contents to the ULA by writing the address and length of the
185 list, along with the display line at which the palette is to be changed, to
186 ULA registers such that the ULA buffers the list and performs the redefinition
187 at the appropriate time. Throughput/bandwidth considerations might impose
188 restrictions on the practical length of such a list, however.
189
190 Palette-Free Modes
191 ------------------
192
193 Palette-free modes might be defined where bit values directly correspond to
194 the red, green and blue channels, although this would mostly make sense only
195 for modes with depths greater than the standard 4 bits per pixel, and such
196 modes would require more memory than MODE 2 if they were to have an acceptable
197 resolution.
198
199 Display Suspend
200 ---------------
201
202 Especially when writing to the screen memory, it could be beneficial to be
203 able to suspend the ULA's access to the memory, instead producing blank values
204 for all screen pixels until a program is ready to reveal the screen. This is
205 different from palette blanking since with a blank palette, the ULA is still
206 reading screen memory and translating its contents into pixel values that end
207 up being blank.
208
209 This function is reminiscent of a capability of the ZX81, albeit necessary on
210 that hardware to reduce the load on the system CPU which was responsible for
211 producing the video output.
212
213 Hardware Sprites
214 ----------------
215
216 An enhanced ULA might provide hardware sprites, but this would be done in an
217 way that is incompatible with the standard ULA, since no &FE*X locations are
218 available for allocation. To keep the facility simple, hardware sprites would
219 have a standard byte width and height.
220
221 The specification of sprites could involve the reservation of 16 locations
222 (for example, &FE20-F) specifying a fixed number of eight sprites, with each
223 location pair referring to the sprite data. By limiting the ULA to dealing
224 with a fixed number of sprites, the work required inside the ULA would be
225 reduced since it would avoid having to deal with arbitrary numbers of sprites.
226
227 The principal limitation on providing hardware sprites is that of having to
228 obtain sprite data, given that the ULA is usually required to retrieve screen
229 data, and given the lack of memory bandwidth available to retrieve sprite data
230 (particularly from multiple sprites supposedly at the same position) and
231 screen data simultaneously. Although the ULA could potentially read sprite
232 data and screen data in alternate memory accesses in screen modes where the
233 bandwidth is not already fully utilised, this would result in a degradation of
234 performance.
235
236 Additional Screen Mode Configurations
237 -------------------------------------
238
239 Alternative screen mode configurations could be supported. The ULA has to
240 produce 640 pixel values across the screen, with pixel doubling or quadrupling
241 employed to fill the screen width:
242
243 Screen width Columns Scaling Depth Bytes
244 ------------ ------- ------- ----- -----
245 640 80 x1 1 80
246 320 40 x2 1, 2 40, 80
247 160 20 x4 2, 4 40, 80
248
249 It must also use at most 80 byte-sized memory accesses to provide the
250 information for the display. Given that characters must occupy an 8x8 pixel
251 array, if a configuration featuring anything other than 20, 40 or 80 character
252 columns is to be supported, compromises must be made such as the introduction
253 of blank pixels either between characters (such as occurs between rows in MODE
254 3 and 6) or at the end of a scanline (such as occurs at the end of the frame
255 in MODE 3 and 6). Consider the following configuration:
256
257 Screen width Columns Scaling Depth Bytes Blank
258 ------------ ------- ------- ----- ------ -----
259 208 26 x3 1, 2 26, 52 16
260
261 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4
262 colours could be provided, with 16 blank pixel values (out of a total of 640)
263 generated either at the start or end (or split between the start and end) of
264 each scanline.
265
266 Character Attributes
267 --------------------
268
269 The BBC Micro MODE 7 employs something resembling character attributes to
270 support teletext displays, but depends on circuitry providing a character
271 generator. The ZX Spectrum, on the other hand, provides character attributes
272 as a means of colouring bitmapped graphics. Although such a feature is very
273 limiting as the sole means of providing multicolour graphics, in situations
274 where the choice is between low resolution multicolour graphics or high
275 resolution monochrome graphics, character attributes provide a potentially
276 useful compromise.
277
278 For each byte read, the ULA must deliver 8 pixel values (out of a total of
279 640) to the video output, doing so by either emptying its pixel buffer on a
280 pixel per cycle basis, or by multiplying pixels and thus holding them for more
281 than one cycle. For example for a screen mode having 640 pixels in width:
282
283 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
284 Reads: B B
285 Pixels: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
286
287 And for a screen mode having 320 pixels in width:
288
289 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
290 Reads: B
291 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
292
293 However, in modes where less than 80 bytes are required to generate the pixel
294 values, an enhanced ULA might be able to read additional bytes between those
295 providing the bitmapped graphics data:
296
297 Cycle: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
298 Reads: B A
299 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
300
301 These additional bytes could provide colour information for the bitmapped data
302 in the following character column (of 8 pixels). Since it would be desirable
303 to apply attribute data to the first column, the initial 8 cycles might be
304 configured to not produce pixel values.
305
306 For an entire character, attribute data need only be read for the first row of
307 pixels for a character. The subsequent rows would have attribute information
308 applied to them, although this would require the attribute data to be stored
309 in some kind of buffer. Thus, the following access pattern would be observed:
310
311 Cycle: A B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ... _ B ...
312
313 A whole byte used for colour information for a whole character would result in
314 a choice of 256 colours, and this might be somewhat excessive. By only reading
315 attribute bytes at every other opportunity, a choice of 16 colours could be
316 applied individually to two characters.
317
318 Cycle: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
319 Reads: B A B -
320 Pixels: 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
321
322 Further reductions in attribute data access, offering 4 colours for every
323 character in a four character block, for example, might also be worth
324 considering.
325
326 Consider the following configurations for screen modes with a colour depth of
327 1 bit per pixel for bitmap information:
328
329 Screen width Columns Scaling Bytes (B) Bytes (A) Colours Screen start
330 ------------ ------- ------- --------- --------- ------- ------------
331 320 40 x2 40 40 256 &5300
332 320 40 x2 40 20 16 &5580 -> &5500
333 320 40 x2 40 10 4 &56C0 -> &5600
334 208 26 x3 26 26 256 &62C0 -> &6200
335 208 26 x3 26 13 16 &6460 -> &6400
336
337 MODE 7 Emulation using Character Attributes
338 -------------------------------------------
339
340 If the scheme of applying attributes to character regions were employed to
341 emulate MODE 7, in conjunction with the MODE 6 display technique, the
342 following configuration would be required:
343
344 Screen width Columns Rows Bytes (B) Bytes (A) Colours Screen start
345 ------------ ------- ---- --------- --------- ------- ------------
346 320 40 25 40 20 16 &5ECC -> &5E00
347 320 40 25 40 10 4 &5FC6 -> &5F00
348
349 Although this requires much more memory than MODE 7 (8500 bytes versus MODE
350 7's 1000 bytes), it does not need much more memory than MODE 6, and it would
351 at least make a limited 40-column multicolour mode available as a substitute
352 for MODE 7.
353
354 Enhanced Graphics and Mode Layouts
355 ----------------------------------
356
357 Screen modes with different screen memory mappings, higher resolutions and
358 larger colour depths might be possible, but this would in most cases involve
359 the allocation of more screen memory, and the ULA would probably then be
360 obliged to page in such memory for the CPU to be able to sensibly access it
361 all. Merely changing the memory mappings in order to have Archimedes-style
362 row-oriented screen addresses (instead of character-oriented addresses) could
363 be done for the existing modes, but this might not be sufficiently beneficial,
364 especially since accessing regions of the screen would involve incrementing
365 pointers by amounts that are inconvenient on an 8-bit CPU.
366
367 Enhanced Sound
368 --------------
369
370 The standard ULA reserves &FE*6 for sound generation and cassette
371 input/output, thus making it impossible to support multiple channels within
372 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,
373 and an enhanced ULA could adopt this interface.
374
375 The BBC Micro uses the SN76489 chip to produce sound, and the entire
376 functionality of this chip could be emulated for enhanced sound, with a subset
377 of the functionality exposed via the &FE*6 interface.
378
379 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489
380
381 Waveform Upload
382 ---------------
383
384 As with a hardware sprite function, waveforms could be uploaded or referenced
385 using locations as registers referencing memory regions.
386
387 BBC ULA Compatibility
388 ---------------------
389
390 Although some new ULA functions could be defined in a way that is also
391 compatible with the BBC Micro, the BBC ULA is itself incompatible with the
392 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory
393 map, but controls various functions specific to the 6845 video controller;
394 &FE08-F is reserved for the serial controller. It therefore becomes possible
395 to disregard compatibility where compatibility is already disregarded for a
396 particular area of functionality.
397
398 &FE20-F maps to video ULA functionality on the BBC Micro which provides
399 control over the palette (using address &FE21, compared to &FE07-F on the
400 Electron) and other system-specific functions. Since the location usage is
401 generally incompatible, this region could be reused for other purposes.
402
403 ULA Pin Functions
404 -----------------
405
406 The functions of the ULA pins are described in the Electron Service Manual. Of
407 interest to video processing are the following:
408
409 CSYNC (low during horizontal or vertical synchronisation periods, high
410 otherwise)
411
412 HS (low during horizontal synchronisation periods, high otherwise)
413
414 RED, GREEN, BLUE (pixel colour outputs)
415
416 CLOCK IN (a 16MHz clock input, 4V peak to peak)
417
418 PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)
419
420 More general memory access pins:
421
422 RAM0...RAM3 (data lines to/from the RAM)
423
424 RA0...RA7 (address lines for sending both row and column addresses to the RAM)
425
426 RAS (row address strobe setting the row address on a negative edge - see the
427 timing notes)
428
429 CAS (column address strobe setting the column address on a negative edge -
430 see the timing notes)
431
432 WE (sets write enable with logic 0, read with logic 1)
433
434 ROM (select data access from ROM)
435
436 CPU-oriented memory access pins:
437
438 A0...A15 (CPU address lines)
439
440 PD0...PD7 (CPU data lines)
441
442 R/W (indicates CPU write with logic 0, CPU read with logic 1)
443
444 Interrupt-related pins:
445
446 NMI (CPU request for uninterrupted 1MHz access to memory)
447
448 IRQ (signal event to CPU)
449
450 POR (power-on reset, resetting the ULA on a positive edge and asserting the
451 CPU's RST pin)
452
453 RST (master reset for the CPU signalled on power-up and by the Break key)
454
455 Keyboard-related pins:
456
457 KBD0...KBD3 (keyboard inputs)
458
459 CAPS LOCK (control status LED)
460
461 Sound-related pins:
462
463 SOUND O/P (sound output using internal oscillator)
464
465 Cassette-related pins:
466
467 CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)
468
469 CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)
470
471 CAS RC (detect high tone)
472
473 CAS MO (motor relay output)
474
475 ÷13 IN (~1200 baud clock input)