ULA

ULA.txt

116:69f0c87496c6
7 months ago Paul Boddie Added some notes about RAM access and the limitations applying to the CPU.
     1 The Acorn Electron ULA     2 ======================     3      4 Principal Design and Feature Constraints     5 ----------------------------------------     6      7 The features of the ULA are limited in sophistication by the amount of time     8 and resources that can be allocated to each activity supporting the     9 fundamental features and obligations of the unit. Maintaining a screen display    10 based on the contents of RAM itself requires the ULA to have exclusive access    11 to various hardware resources for a significant period of time.    12     13 Whilst other elements of the ULA can in principle run in parallel with the    14 display refresh activity, they cannot also access the RAM at the same time.    15 Consequently, other features that might use the RAM must accept a reduced    16 allocation of that resource in comparison to a hypothetical architecture where    17 concurrent RAM access is possible at all times.    18     19 Thus, the principal constraint for many features is bandwidth. The duration of    20 access to hardware resources is one aspect of this; the rate at which such    21 resources can be accessed is another. For example, the RAM is not fast enough    22 to support access more frequently than one byte per 2MHz cycle, and for screen    23 modes involving 80 bytes of screen data per scanline, there are no free cycles    24 for anything other than the production of pixel output during the active    25 scanline periods.    26     27 Another constraint is imposed by the method of RAM access provided by the ULA.    28 The ULA is able to access RAM by fetching 4 bits at a time and thus managing    29 to transfer 8 bits within a single 2MHz cycle, this being sufficient to    30 provide display data for the most demanding screen modes. However, this    31 mechanism's timing requirements are beyond the capabilities of the CPU when    32 running at 2MHz.    33     34 Consequently, the CPU will only ever be able to access RAM via the ULA at    35 1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to    36 refresh the display, the ULA is still able to make use of the idle part of    37 each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself    38 access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz    39 cycle), thus supporting the less demanding screen modes.    40     41 Timing    42 ------    43     44 According to 15.3.2 in the Advanced User Guide, there are 312 scanlines, 256    45 of which are used to generate pixel data. At 50Hz, this means that 128 cycles    46 are spent on each scanline (2000000 cycles / 50 = 40000 cycles; 40000 cycles /    47 312 ~= 128 cycles). This is consistent with the observation that each scanline    48 requires at most 80 bytes of data, and that the ULA is apparently busy for 40    49 out of 64 microseconds in each scanline.    50     51 (In fact, since the ULA is seeking to provide an image for an interlaced    52 625-line display, there are in fact two "fields" involved, one providing 312    53 scanlines and one providing 313 scanlines. See below for a description of the    54 video system.)    55     56 Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7,    57 each providing two bits of each byte) using two cycles within the 500ns period    58 of the 2MHz clock to complete each access operation. Since the CPU and ULA    59 have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must    60 effectively run at 1MHz (since every other 500ns period involves the ULA    61 accessing RAM) during transfers of screen data.    62     63 The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided    64 by the ULA (IC1) depending on the screen mode in use.  Each 16MHz cycle is    65 approximately 62.5ns. To access the memory, the following patterns    66 corresponding to 16MHz cycles are required:    67     68      Time (ns):  0-------------- 500------------- ...    69    2 MHz cycle:  0               1                ...    70   16 MHz cycle:  0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7  ...    71                  /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ ...    72           ~RAS:  /---\___________/---\___________ ...    73           ~CAS:  /-----\___/-\___/-----\___/-\___ ...    74 Address events:      A B     C       A B     C    ...    75    Data events:           F     S         F     S ...    76     77       ~RAS ops:  1   0           1   0            ...    78       ~CAS ops:  1     0   1 0   1     0   1 0    ...    79     80    Address ops:     a b     c       a b     c     ...    81       Data ops:  s         f     s         f      ...    82     83            ~WE:  ......W                          ...    84        PHI OUT:  \_______________/--------------- ...    85      CPU (RAM):  L               D                ...    86            RnW:  R                                ...    87     88        PHI OUT:  \_______/-------\_______/------- ...    89      CPU (ROM):  L       D       L       D        ...    90            RnW:          R               R        ...    91     92 ~RAS must be high for 100ns, ~CAS must be high for 50ns.    93 ~RAS must be low for 150ns, ~CAS must be low for 90ns.    94 Data is available 150ns after ~RAS goes low, 90ns after ~CAS goes low.    95     96 Here, "A" and "B" respectively indicate the row and first column addresses    97 being latched into the RAM (on a negative edge for ~RAS and ~CAS    98 respectively), and "C" indicates the second column address being latched into    99 the RAM. Presumably, the first and second half-bytes can be read at "F" and   100 "S" respectively, and the row and column addresses must be made available at   101 "a" and "b" (and "c") respectively at the latest. Data can be read at "f" and   102 "s" for the first and second half-bytes respectively.   103    104 For the CPU, "L" indicates the point at which an address is taken from the CPU   105 address bus, on a negative edge of PHI OUT, with "D" being the point at which   106 data may either be read or be asserted for writing, on a positive edge of PHI   107 OUT. Here, PHI OUT is driven at 1MHz. Given that ~WE needs to be driven low   108 for writing or high for reading, and thus propagates RnW from the CPU, this   109 would need to be done before data would be retrieved and, according to the   110 TM4164EC4 datasheet, even as late as the column address is presented and ~CAS   111 brought low.   112    113 The TM4164EC4-15 has a row address access time of 150ns (maximum) and a column   114 address access time of 90ns (maximum), which appears to mean that ~RAS must be   115 held low for at least 150ns and that ~CAS must be held low for at least 90ns   116 before data becomes available. 150ns is 2.4 cycles (at 16MHz) and 90ns is 1.44   117 cycles. Thus, "A" to "F" is 2.5 cycles, "B" to "F" is 1.5 cycles, "C" to "S"   118 is 1.5 cycles.   119    120 Note that the Service Manual refers to the negative edge of RAS and CAS, but   121 the datasheet for the similar TM4164EC4 product shows latching on the negative   122 edge of ~RAS and ~CAS. It is possible that the Service Manual also intended to   123 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that   124 "page mode" provides the appropriate behaviour for that particular product.   125    126 The CPU, when accessing the RAM alone, apparently does not make use of the   127 vacated "slot" that the ULA would otherwise use (when interleaving accesses in   128 MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when   129 accessing ROM (and potentially sideways RAM). The principal limitation is the   130 amount of time needed between issuing an address and receiving an entire byte   131 from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the   132 4 cycles that would be required for 2MHz operation.   133    134 See: Acorn Electron Advanced User Guide   135 See: Acorn Electron Service Manual   136      http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf   137 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm   138 See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438   139    140 CPU Clock Notes   141 ---------------   142    143 "The 6502 receives an external square-wave clock input signal on pin 37, which   144 is usually labeled PHI0. [...] This clock input is processed within the 6502   145 to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2   146 is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been   147 through two inverters and a push-pull amplifier. The same network of   148 transistors within the 6502 which generates PHI2 is also tied to PHI1, and   149 generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made   150 available to external devices is so that they know when they can access the   151 CPU. When PHI1 is high, this means that external devices can read from the   152 address bus or data bus; when PHI2 is high, this means that external devices   153 can write to the data bus."   154    155 See: http://lateblt.livejournal.com/88105.html   156    157 "The 6502 has a synchronous memory bus where the master clock is divided into   158 two phases (Phase 1 and Phase 2). The address is always generated during Phase   159 1 and all memory accesses take place during Phase 2."   160    161 See: http://www.jmargolin.com/vgens/vgens.htm   162    163 Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During   164 Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means   165 when PHI1 is high.   166    167 Bandwidth Figures   168 -----------------   169    170 Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312   171 total lines, with 80 cycles occurring in the active periods of display   172 scanlines, the following bandwidth calculations can be performed:   173    174 Total theoretical maximum:   175        128 cycles * 312 lines   176      = 39936 bytes   177    178 MODE 0, 1, 2:   179 ULA:    80 cycles * 256 lines   180      = 20480 bytes   181 CPU:    48 cycles / 2 * 256 lines   182      + 128 cycles / 2 * (312 - 256) lines   183      = 9728 bytes   184    185 MODE 3:   186 ULA:    80 cycles * 24 rows * 8 lines   187      = 15360 bytes   188 CPU:    48 cycles / 2 * 24 rows * 8 lines   189      + 128 cycles / 2 * (312 - (24 rows * 8 lines))   190      = 12288 bytes   191    192 MODE 4, 5:   193 ULA:    40 cycles * 256 lines   194      = 10240 bytes   195 CPU:   (40 cycles + 48 cycles / 2) * 256 lines   196      + 128 cycles / 2 * (312 - 256) lines   197      = 19968 bytes   198    199 MODE 6:   200 ULA:    40 cycles * 24 rows * 8 lines   201      = 7680 bytes   202 CPU:   (40 cycles + 48 cycles / 2) * 24 rows * 8 lines   203      + 128 cycles / 2 * (312 - (24 rows * 8 lines))   204      = 19968 bytes   205    206 Here, the division of 2 for CPU accesses is performed to indicate that the CPU   207 only uses every other access opportunity even in uncontended periods. See the   208 2MHz RAM Access enhancement below for bandwidth calculations that consider   209 this limitation removed.   210    211 Video Timing   212 ------------   213    214 According to 8.7 in the Service Manual, and the PAL Wikipedia page,   215 approximately 4.7?s is used for the sync pulse, 5.7?s for the "back porch"   216 (including the "colour burst"), and 1.65?s for the "front porch", totalling   217 12.05?s and thus leaving 51.95?s for the active video signal for each   218 scanline. As the Service Manual suggests in the oscilloscope traces, the   219 display information is transmitted more or less centred within the active   220 video period since the ULA will only be providing pixel data for 40?s in each   221 scanline.   222    223 Each 62.5ns cycle happens to correspond to 64?s divided by 1024, meaning that   224 each scanline can be divided into 1024 cycles, although only 640 at most are   225 actively used to provide pixel data. Pixel data production should only occur   226 within a certain period on each scanline, approximately 262 cycles after the   227 start of hsync:   228    229   active video period = 51.95?s   230   pixel data period = 40?s   231   total silent period = 51.95?s - 40?s = 11.95?s   232   silent periods (before and after) = 11.95?s / 2 = 5.975?s   233   hsync and back porch period = 4.7?s + 5.7?s = 10.4?s   234   time before pixel data period = 10.4?s + 5.975?s = 16.375?s   235   pixel data period start cycle = 16.375?s / 62.5ns = 262   236    237 By choosing a number divisible by 8, the RAM access mechanism can be   238 synchronised with the pixel production. Thus, 256 is a more appropriate start   239 cycle, where the HS (horizontal sync) signal corresponding to the 4?s sync   240 pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages"   241 document) occurs at cycle 0.   242    243 To summarise:   244    245   HS signal starts at cycle 0 on each horizontal scanline   246   HS signal ends approximately 4?s later at cycle 64   247   Pixel data starts approximately 12?s later at cycle 256   248    249 "Re: Electron Memory Contention" provides measurements that appear consistent   250 with these calculations.   251    252 The "vertical blanking period", meaning the period before picture information   253 in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of   254 this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5   255 lines. Thus, the first visible scanline on the first field of a frame occurs   256 half way through the 23rd scanline period measured from the start of vsync   257 (indicated by "V" in the diagrams below):   258    259                                         10                  20    23   260   Line in frame:       1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8   261     Line from 1:       0                                          22 3   262  Line on screen: .:::::VVVVV:::::                                   12233445566   263                   |_________________________________________________|   264                            25 line vertical blanking period   265    266 In the second field of a frame, the first visible scanline coincides with the   267 24th scanline period measured from the start of line 313 in the frame:   268    269                310                                                 336   270   Line in frame: 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9   271   Line from 313:       0                                            23 4   272  Line on screen: 88:::::VVVVV::::                                    11223344   273                288 |                                                 |   274                    |_________________________________________________|   275                             25 line vertical blanking period   276    277 In order to consider only full lines, we might consider the start of each   278 frame to occur 23 lines after the start of vsync.   279    280 Again, it is likely that pixel data production should only occur on scanlines   281 within a certain period on each frame. The "625/50" document indicates that   282 only a certain region is "safe" to use, suggesting a vertically centred region   283 with approximately 15 blank lines above and below the picture. However, the   284 "PAL TV timing and voltages" document suggests 28 blank lines above and below   285 the picture. This would centre the 256 lines within the 312 lines of each   286 field and thus provide a start of picture approximately 5.5 or 5 lines after   287 the end of the blanking period or 28 or 27.5 lines after the start of vsync.   288    289 To summarise:   290    291   CSYNC signal starts at cycle 0   292   CSYNC signal ends approximately 160?s (2.5 lines) later at cycle 2560   293   Start of line occurs approximately 1632?s (5.5 lines) later at cycle 28672   294    295 See: http://en.wikipedia.org/wiki/PAL   296 See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal   297 See: The 625/50 PAL Video Signal and TV Compatible Graphics Modes   298      http://lipas.uwasa.fi/~f76998/video/modes/   299 See: PAL TV timing and voltages   300      http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/   301 See: Line Standards   302      http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html   303 See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards   304      http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf   305 See: Re: Electron Memory Contention   306      http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109   307    308 RAM Integrated Circuits   309 -----------------------   310    311 Unicorn Electronics appears to offer 4164 RAM chips (as well as 6502 series   312 CPUs such as the 6502, 6502A, 6502B and 65C02). These 4164 devices are   313 available in 100ns (4164-100), 120ns (4164-120) and 150ns (4164-150) variants,   314 have 16 pins and address 65536 bits through a 1-bit wide channel. Similarly,   315 ByteDelight.com sell 4164 devices primarily for the ZX Spectrum.   316    317 The documentation for the Electron mentions 4164-15 RAM chips for IC4-7, and   318 the Samsung-produced KM41464 series is apparently equivalent to the Texas   319 Instruments 4164 chips presumably used in the Electron.   320    321 The TM4164EC4 series combines 4 64K x 1b units into a single package and   322 appears similar to the TM4164EA4 featured on the Electron's circuit diagram   323 (in the Advanced User Guide but not the Service Manual), and it also has 22   324 pins providing 3 additional inputs and 3 additional outputs over the 16 pins   325 of the individual 4164-15 modules, presumably allowing concurrent access to   326 the packaged memory units.   327    328 As far as currently available replacements are concerned, the NTE4164 is a   329 potential candidate: according to the Vetco Electronics entry, it is   330 supposedly a replacement for the TMS4164-15 amongst many other parts. Similar   331 parts include the NTE2164 and the NTE6664, both of which appear to have   332 largely the same performance and connection characteristics. Meanwhile, the   333 NTE21256 appears to be a 16-pin replacement with four times the capacity that   334 maintains the single data input and output pins. Using the NTE21256 as a   335 replacement for all ICs combined would be difficult because of the single bit   336 output.   337    338 Another device equivalent to the 4164-15 appears to be available under the   339 code 41662 from Jameco Electronics as the Siemens HYB 4164-2. The Jameco Web   340 site lists data sheets for other devices on the same page, but these are   341 different and actually appear to be provided under the 41574 product code (but   342 are listed under 41464-10) and appear to be replacements for the TM4164EC4:   343 the Samsung KM41464A-15 and NEC ?PD41464 employ 18 pins, eliminating 4 pins by   344 employing 4 pins for both input and output.   345    346             Pins    I/O pins    Row access  Column access   347             ----    --------    ----------  -------------   348 TM4164EC4   22      4 + 4       150ns (15)  90ns (15)   349 KM41464AP   18      4           150ns (15)  75ns (15)   350 NTE21256    16      1 + 1       150ns       75ns   351 HYB 4164-2  16      1 + 1       150ns       100ns   352 ?PD41464    18      4           120ns (12)  60ns (12)   353    354 See: TM4164EC4 65,536 by 4-Bit Dynamic RAM Module   355      http://www.datasheetarchive.com/dl/Datasheets-112/DSAP0051030.pdf   356 See: Dynamic RAMS   357      http://www.unicornelectronics.com/IC/DYNAMIC.html   358 See: New old stock 8x 4164 chips   359      http://www.bytedelight.com/?product=8x-4164-chips-new-old-stock   360 See: KM4164B 64K x 1 Bit Dynamic RAM with Page Mode   361      http://images.ihscontent.net/vipimages/VipMasterIC/IC/SAMS/SAMSD020/SAMSD020-45.pdf   362 See: NTE2164 Integrated Circuit 65,536 X 1 Bit Dynamic Random Access Memory   363      http://www.vetco.net/catalog/product_info.php?products_id=2806   364 See: NTE4164 - IC-NMOS 64K DRAM 150NS   365      http://www.vetco.net/catalog/product_info.php?products_id=3680   366 See: NTE21256 - IC-256K DRAM 150NS   367      http://www.vetco.net/catalog/product_info.php?products_id=2799   368 See: NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)   369      http://www.nteinc.com/specs/21000to21999/pdf/nte21256.pdf   370 See: NTE6664 - IC-MOS 64K DRAM 150NS   371      http://www.vetco.net/catalog/product_info.php?products_id=5213   372 See: NTE6664 Integrated Circuit 64K-Bit Dynamic RAM   373      http://www.nteinc.com/specs/6600to6699/pdf/nte6664.pdf   374 See: 4164-150: MAJOR BRANDS   375      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41662_-1   376 See: HYB 4164-1, HYB 4164-2, HYB 4164-3 65,536-Bit Dynamic Random Access Memory (RAM)   377      http://www.jameco.com/Jameco/Products/ProdDS/41662SIEMENS.pdf   378 See: KM41464A NMOS DRAM 64K x 4 Bit Dynamic RAM with Page Mode   379      http://www.jameco.com/Jameco/Products/ProdDS/41662SAM.pdf   380 See: NEC ?41464 65,536 x 4-Bit Dynamic NMOS RAM   381      http://www.jameco.com/Jameco/Products/ProdDS/41662NEC.pdf   382 See: 41464-10: MAJOR BRANDS   383      http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_41574_-1   384    385 Interrupts   386 ----------   387    388 The ULA generates IRQs (maskable interrupts) according to certain conditions   389 and these conditions are controlled by location &FE00:   390    391   * Vertical sync (bottom of displayed screen)   392   * 50MHz real time clock   393   * Transmit data empty   394   * Receive data full   395   * High tone detect   396    397 The ULA is also used to clear interrupt conditions through location &FE05. Of   398 particular significance is bit 7, which must be set if an NMI (non-maskable   399 interrupt) has occurred and has thus suspended ULA access to memory, restoring   400 the normal function of the ULA.   401    402 ROM Paging   403 ----------   404    405 Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM   406 mappings exist:   407    408    8    keyboard   409    9    keyboard (duplicate)   410   10    BASIC ROM   411   11    BASIC ROM (duplicate)   412    413 Paging in a ROM involves the following procedure:   414    415  1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to   416     2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is   417     selected.   418  2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero   419     whilst writing the desired ROM number n in bits 0 to 2.   420    421 See: http://stardot.org.uk/forums/viewtopic.php?p=136686#p136686   422    423 Shadow/Expanded Memory   424 ----------------------   425    426 The Electron exposes all sixteen address lines and all eight data lines   427 through the expansion bus. Using such lines, it is possible to provide   428 additional memory - typically sideways ROM and RAM - on expansion cards and   429 through cartridges, although the official cartridge specification provides   430 fewer address lines and only seeks to provide access to memory in 16K units.   431    432 Various modifications and upgrades were developed to offer "turbo"   433 capabilities to the Electron, permitting the CPU to access a separate 8K of   434 RAM at 2MHz, presumably preventing access to the low 8K of RAM accessible via   435 the ULA through additional logic. However, an enhanced ULA might support   436 independent CPU access to memory over the expansion bus by allowing itself to   437 be discharged from providing access to memory, potentially for a range of   438 addresses, and for the CPU to communicate with external memory uninterrupted.   439    440 Sideways RAM/ROM and Upper Memory Access   441 ----------------------------------------   442    443 Although the ULA controls the CPU clock, effectively slowing or stopping the   444 CPU when the ULA needs to access screen memory, it is apparently able to allow   445 the CPU to access addresses of &8000 and above - the upper region of memory -   446 at 2MHz independently of any access to RAM that the ULA might be performing,   447 only blocking the CPU if it attempts to access addresses of &7FFF and below   448 during any ULA memory access - the lower region of memory - by stopping or   449 stalling its clock.   450    451 Thus, the ULA remains aware of the level of the A15 line, only inhibiting the   452 CPU clock if the line goes low, when the CPU is attempting to access the lower   453 region of memory.   454    455 Hardware Scrolling (and Enhancement)   456 ------------------------------------   457    458 On the standard ULA, &FE02 and &FE03 map to a 9 significant bits address with   459 the least significant 5 bits being zero, thus limiting the scrolling   460 resolution to 64 bytes. An enhanced ULA could support a resolution of 2 bytes   461 using the same layout of these addresses.   462    463 |--&FE02--------------| |--&FE03--------------|   464 XX XX 14 13 12 11 10 09 08 07 06 XX XX XX XX XX   465    466    XX 14 13 12 11 10 09 08 07 06 05 04 03 02 01 XX   467    468 Arguably, a resolution of 8 bytes is more useful, since the mapping of screen   469 memory to pixel locations is character oriented. A change in 8 bytes would   470 permit a horizontal scrolling resolution of 2 pixels in MODE 2, 4 pixels in   471 MODE 1 and 5, and 8 pixels in MODE 0, 3 and 6. This resolution is actually   472 observed on the BBC Micro (see 18.11.2 in the BBC Microcomputer Advanced User   473 Guide).   474    475 One argument for a 2 byte resolution is smooth vertical scrolling. A pitfall   476 of changing the screen address by 2 bytes is the change in the number of lines   477 from the initial and final character rows that need reading by the ULA, which   478 would need to maintain this state information (although this is a relatively   479 trivial change). Another pitfall is the complication that might be introduced   480 to software writing bitmaps of character height to the screen.   481    482 See: http://pastraiser.com/computers/acornelectron/acornelectron.html   483    484 Enhancement: Mode Layouts   485 -------------------------   486    487 Merely changing the screen memory mappings in order to have Archimedes-style   488 row-oriented screen addresses (instead of character-oriented addresses) could   489 be done for the existing modes, but this might not be sufficiently beneficial,   490 especially since accessing regions of the screen would involve incrementing   491 pointers by amounts that are inconvenient on an 8-bit CPU.   492    493 However, instead of using a Archimedes-style mapping, column-oriented screen   494 addresses could be more feasibly employed: incrementing the address would   495 reference the vertical screen location below the currently-referenced location   496 (just as occurs within characters using the existing ULA); instead of   497 returning to the top of the character row and referencing the next horizontal   498 location after eight bytes, the address would reference the next character row   499 and continue to reference locations downwards over the height of the screen   500 until reaching the bottom; at the bottom, the next location would be the next   501 horizontal location at the top of the screen.   502    503 In other words, the memory layout for the screen would resemble the following   504 (for MODE 2):   505    506   &3000 &3100       ... &7F00   507   &3001 &3101   508   ...   ...   509   &3007   510   &3008   511   ...   512   ...                   ...   513   &30FF             ... &7FFF   514    515 Since there are 256 pixel rows, each column of locations would be addressable   516 using the low byte of the address. Meanwhile, the high byte would be   517 incremented to address different columns. Thus, addressing screen locations   518 would become a lot more convenient and potentially much more efficient for   519 certain kinds of graphical output.   520    521 One potential complication with this simplified addressing scheme arises with   522 hardware scrolling. Vertical hardware scrolling by one pixel row (not supported   523 with the existing ULA) would be achieved by incrementing or decrementing the   524 screen start address; by one character row, it would involve adding or   525 subtracting 8. However, the ULA only supports multiples of 64 when changing the   526 screen start address. Thus, if such a scheme were to be adopted, three   527 additional bits would need to be supported in the screen start register (see   528 "Hardware Scrolling (and Enhancement)" for more details). However, horizontal   529 scrolling would be much improved even under the severe constraints of the   530 existing ULA: only adjustments of 256 to the screen start address would be   531 required to produce single-location scrolling of as few as two pixels in MODE 2   532 (four pixels in MODEs 1 and 5, eight pixels otherwise).   533    534 More disruptive is the effect of this alternative layout on software.   535 Presumably, compatibility with the BBC Micro was the primary goal of the   536 Electron's hardware design. With the character-oriented screen layout in   537 place, system software (and application software accessing the screen   538 directly) would be relying on this layout to run on the Electron with little   539 or no modification. Although it might have been possible to change the system   540 software to use this column-oriented layout instead, this would have incurred   541 a development cost and caused additional work porting things like games to the   542 Electron. Moreover, a separate branch of the software from that supporting the   543 BBC Micro and closer derivatives would then have needed maintaining.   544    545 The decision to use the character-oriented layout in the BBC Micro may have   546 been related to the choice of circuitry and to facilitate a convenient   547 hardware implementation, and by the time the Electron was planned, it was too   548 late to do anything about this somewhat unfortunate choice.   549    550 Pixel Layouts   551 -------------   552    553 The pixel layouts are as follows:   554    555   Modes         Depth (bpp)     Pixels (from bits)   556   -----         -----------     ------------------   557   0, 3, 4, 6    1               7 6 5 4 3 2 1 0   558   1, 5          2               73 62 51 40   559   2             4               7531 6420   560    561 Since the ULA reads a half-byte at a time, one might expect it to attempt to   562 produce pixels for every half-byte, as opposed to handling entire bytes.   563 However, the pixel layout is not conducive to producing pixels as soon as a   564 half-byte has been read for a given full-byte location: in 1bpp modes the   565 first four pixels can indeed be produced, but in 2bpp and 4bpp modes the pixel   566 data is spread across the entire byte in different ways.   567    568 An alternative arrangement might be as follows:   569    570   Modes         Depth (bpp)     Pixels (from bits)   571   -----         -----------     ------------------   572   0, 3, 4, 6    1               7 6 5 4 3 2 1 0   573   1, 5          2               76 54 32 10   574   2             4               7654 3210   575    576 Just as the mode layouts were presumably decided by compatibility with the BBC   577 Micro, the pixel layouts will have been maintained for similar reasons.   578 Unfortunately, this layout prevents any optimisation of the ULA for handling   579 half-byte pixel data generally.   580    581 Enhancement: The Missing MODE 4   582 -------------------------------   583    584 The Electron inherits its screen mode selection from the BBC Micro, where MODE   585 3 is a text version of MODE 0, and where MODE 6 is a text version of MODE 4.   586 Neither MODE 3 nor MODE 6 is a genuine character-based text mode like MODE 7,   587 however, and they are merely implemented by skipping two scanlines in every   588 ten after the eight required to produce a character line. Thus, such modes   589 provide a 24-row display.   590    591 In principle, nothing prevents this "text mode" effect being applied to other   592 modes. The 20-column modes are not well-suited to displaying text, which   593 leaves MODE 1 which, unlike MODEs 3 and 6, can display 4 colours rather than   594 2. Although the need for a non-monochrome 40-column text mode is addressed by   595 MODE 7 on the BBC Micro, the Electron lacks such a mode.   596    597 If the 4-colour, 24-row variant of MODE 1 were to be provided, logically it   598 would occupy MODE 4 instead of the current MODE 4:   599    600   Screen mode  Size (kilobytes)  Colours  Rows  Resolution   601   -----------  ----------------  -------  ----  ----------   602   0            20                2        32    640x256   603   1            20                4        32    320x256   604   2            20                16       32    160x256   605   3            16                2        24    640x256   606   4 (new)      16                4        24    320x256   607   4 (old)      10                2        32    320x256   608   5            10                4        32    160x256   609   6            8                 2        24    320x256   610    611 Thus, for increasing mode numbers, the size of each mode would be the same or   612 less than the preceding mode.   613    614 Enhancement: 2MHz RAM Access   615 ----------------------------   616    617 Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU   618 when not competing with the ULA only accesses RAM every other 2MHz cycle (as   619 if the ULA still needed to access the RAM), one useful enhancement would be a   620 mechanism to let the CPU take over the ULA cycles outside the ULA's period of   621 activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to   622 3.   623    624 Thus, the RAM access cycles would resemble the following in MODE 0 to 3:   625    626   Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)   627   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)   628    629 In MODE 4 to 6:   630     631   Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)   632   On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)   633    634 This would improve CPU bandwidth as follows:   635    636                 Standard ULA    Enhanced ULA   637 MODE 0, 1, 2    9728 bytes      19456 bytes   638 MODE 3          12288 bytes     24576 bytes   639 MODE 4, 5       19968 bytes     29696 bytes   640 MODE 6          19968 bytes     32256 bytes   641    642 (Here, the uncontended 2MHz bandwidth for a display period would be 39936   643 bytes, being 128 cycles per line over 312 lines.)   644    645 With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth   646 because all access opportunities to RAM are doubled. Meanwhile, in the other   647 modes, some CPU accesses occur alongside ULA accesses and thus cannot be   648 doubled, but the CPU bandwidth increase is still significant.   649    650 Unfortunately, the mechanism for accessing the RAM is too slow to provide data   651 within the time constraints of 2MHz operation. There is no time remaining in a   652 2MHz cycle for the CPU to receive and process any retrieved data.   653    654 Enhancement: Region Blanking   655 ----------------------------   656    657 The problem of permitting character-oriented blitting in programs whilst   658 scrolling the screen by sub-character amounts could be mitigated by permitting   659 a region of the display to be blank, such as the final lines of the display.   660 Consider the following vertical scrolling by 2 bytes that would cause an   661 initial character row of 6 lines and a final character row of 2 lines:   662    663     6 lines - initial, partial character row   664   248 lines - 31 complete rows   665     2 lines - final, partial character row   666    667 If a routine were in use that wrote 8 line bitmaps to the partial character   668 row now split in two, it would be advisable to hide one of the regions in   669 order to prevent content appearing in the wrong place on screen (such as   670 content meant to appear at the top "leaking" onto the bottom). Blanking 6   671 lines would be sufficient, as can be seen from the following cases.   672    673 Scrolling up by 2 lines:   674    675     6 lines - initial, partial character row   676   240 lines - 30 complete rows   677     4 lines - part of 1 complete row   678   -----------------------------------------------------------------   679     4 lines - part of 1 complete row (hidden to maintain 250 lines)   680     2 lines - final, partial character row (hidden)   681    682 Scrolling down by 2 lines:   683    684     2 lines - initial, partial character row   685   248 lines - 31 complete rows   686   ----------------------------------------------------------   687     6 lines - final, partial character row (hidden)   688    689 Thus, in this case, region blanking would impose a 250 line display with the   690 bottom 6 lines blank.   691    692 See the description of the display suspend enhancement for a more efficient   693 way of blanking lines than merely blanking the palette whilst allowing the CPU   694 to perform useful work during the blanking period.   695    696 To control the blanking or suspending of lines at the top and bottom of the   697 display, a memory location could be dedicated to the task: the upper 4 bits   698 could define a blanking region of up to 16 lines at the top of the screen,   699 whereas the lower 4 bits could define such a region at the bottom of the   700 screen. If more lines were required, two locations could be employed, allowing   701 the top and bottom regions to occupy the entire screen.   702    703 Enhancement: Screen Height Adjustment   704 -------------------------------------   705    706 The height of the screen could be configurable in order to reduce screen   707 memory consumption. This is not quite done in MODE 3 and 6 since the start of   708 the screen appears to be rounded down to the nearest page, but by reducing the   709 height by amounts more than a page, savings would be possible. For example:   710    711   Screen width  Depth  Height  Bytes per line  Saving in bytes  Start address   712   ------------  -----  ------  --------------  ---------------  -------------   713   640           1      252     80              320              &3140 -> &3100   714   640           1      248     80              640              &3280 -> &3200   715   320           1      240     40              640              &5A80 -> &5A00   716   320           2      240     80              1280             &3500   717    718 Screen Mode Selection   719 ---------------------   720    721 Bits 3, 4 and 5 of address &FE*7 control the selected screen mode. For a wider   722 range of modes, the other bits of &FE*7 (related to sound, cassette   723 input/output and the Caps Lock LED) would need to be reassigned and bit 0   724 potentially being made available for use.   725    726 Enhancement: Palette Definition   727 -------------------------------   728    729 Since all memory accesses go via the ULA, an enhanced ULA could employ more   730 specific addresses than &FE*X to perform enhanced functions. For example, the   731 palette control is done using &FE*8-F and merely involves selecting predefined   732 colours, whereas an enhanced ULA could support the redefinition of all 16   733 colours using specific ranges such as &FE18-F (colours 0 to 7) and &FE28-F   734 (colours 8 to 15), where a single byte might provide 8 bits per pixel colour   735 specifications similar to those used on the Archimedes.   736    737 The principal limitation here is actually the hardware: the Electron has only   738 a single output line for each of the red, green and blue channels, and if   739 those outputs are strictly digital and can only be set to a "high" and "low"   740 value, then only the existing eight colours are possible. If a modern ULA were   741 able to output analogue values (or values at well-defined points between the   742 high and low values, such as the half-on value supported by the Amstrad CPC   743 series), it would still need to be assessed whether the circuitry could   744 successfully handle and propagate such values. Various sources indicate that   745 only "TTL levels" are supported by the RGB output circuit, and since there are   746 74LS08 AND logic gates involved in the RGB component outputs from the ULA, it   747 is likely that the ULA is expected to provide only "high" or "low" values.   748    749 Short of adding extra outputs from the ULA (either additional red, green and   750 blue outputs or a combined intensity output), another approach might involve   751 some kind of modulation where an output value might be encoded in multiple   752 pulses at a higher frequency than the pixel frequency. However, this would   753 demand additional circuitry outside the ULA, and component RGB monitors would   754 probably not be able to take advantage of this feature; only UHF and composite   755 video devices (the latter with the composite video colour support enabled on   756 the Electron's circuit board) would potentially benefit.   757    758 Flashing Colours   759 ----------------   760    761 According to the Advanced User Guide, "The cursor and flashing colours are   762 entirely generated in software: This means that all of the logical to physical   763 colour map must be changed to cause colours to flash." This appears to suggest   764 that the palette registers must be updated upon the flash counter - read and   765 written by OSBYTE &C1 (193) - reaching zero and that some way of changing the   766 colour pairs to be any combination of colours might be possible, instead of   767 having colour complements as pairs.   768    769 It is conceivable that the interrupt code responsible does the simple thing   770 and merely inverts the current values for any logical colours (LC) for which   771 the associated physical colour (as supplied as the second parameter to the VDU   772 19 call) has the top bit of its four bit value set. These top bits are not   773 recorded in the palette registers but are presumably recorded separately and   774 used to build bitmaps as follows:   775    776   LC  2 colour  4 colour  16 colour  4-bit value for inversion   777   --  --------  --------  ---------  -------------------------   778    0  00010001  00010001  00010001   1, 1, 1   779    1  01000100  00100010  00010001   4, 2, 1   780    2            01000100  00100010      4, 2   781    3            10001000  00100010      8, 2   782    4                      00010001         1   783    5                      00010001         1   784    6                      00100010         2   785    7                      00100010         2   786    8                      01000100         4   787    9                      01000100         4   788   10                      10001000         8   789   11                      10001000         8   790   12                      01000100         4   791   13                      01000100         4   792   14                      10001000         8   793   15                      10001000         8   794    795   Inversion value calculation:   796    797    2 colour formula: 1 << (colour * 2)   798    4 colour formula: 1 << colour   799   16 colour formula: 1 << ((colour & 2) + ((colour & 8) * 2))   800    801 For example, where logical colour 0 has been mapped to a physical colour in   802 the range 8 to 15, a bitmap of 00010001 would be chosen as its contribution to   803 the inversion operation. (The lower three bits of the physical colour would be   804 used to set the underlying colour information affected by the inversion   805 operation.)   806    807 An operation in the interrupt code would then combine the bitmaps for all   808 logical colours in 2 and 4 colour modes, with the 16 colour bitmaps being   809 combined for groups of logical colours as follows:   810    811    Logical colours   812    ---------------   813    0,  2,  8, 10   814    4,  6, 12, 14   815    5,  7, 13, 15   816    1,  3,  9, 11   817    818 These combined bitmaps would be EORed with the existing palette register   819 values in order to perform the value inversion necessary to produce the   820 flashing effect.   821    822 Thus, in the VDU 19 operation, the appropriate inversion value would be   823 calculated for the logical colour, and this value would then be combined with   824 other inversion values in a dedicated memory location corresponding to the   825 colour's group as indicated above. Meanwhile, the palette channel values would   826 be derived from the lower three bits of the specified physical colour and   827 combined with other palette data in dedicated memory locations corresponding   828 to the palette registers.   829    830 Interestingly, although flashing colours on the BBC Micro are controlled by   831 toggling bit 0 of the &FE20 control register location for the Video ULA, the   832 actual colour inversion is done in hardware.   833    834 Enhancement: Palette Definition Lists   835 -------------------------------------   836    837 It can be useful to redefine the palette in order to change the colours   838 available for a particular region of the screen, particularly in modes where   839 the choice of colours is constrained, and if an increased colour depth were   840 available, palette redefinition would be useful to give the illusion of more   841 than 16 colours in MODE 2. Traditionally, palette redefinition has been done   842 by using interrupt-driven timers, but a more efficient approach would involve   843 presenting lists of palette definitions to the ULA so that it can change the   844 palette at a particular display line.   845    846 One might define a palette redefinition list in a region of memory and then   847 communicate its contents to the ULA by writing the address and length of the   848 list, along with the display line at which the palette is to be changed, to   849 ULA registers such that the ULA buffers the list and performs the redefinition   850 at the appropriate time. Throughput/bandwidth considerations might impose   851 restrictions on the practical length of such a list, however.   852    853 Enhancement: Display Synchronisation Interrupts   854 -----------------------------------------------   855    856 When completing each scanline of the display, the ULA could trigger an   857 interrupt. Since this might impact system performance substantially, the   858 feature would probably need to be configurable, and it might be sufficient to   859 have an interrupt only after a certain number of display lines instead.   860 Permitting the CPU to take action after eight lines would allow palette   861 switching and other effects to occur on a character row basis.   862    863 The ULA provides an interrupt at the end of the display period, presumably so   864 that software can schedule updates to the screen, avoid flickering or tearing,   865 and so on. However, some applications might benefit from an interrupt at, or   866 just before, the start of the display period so that palette modifications or   867 similar effects could be scheduled.   868    869 Enhancement: Palette-Free Modes   870 -------------------------------   871    872 Palette-free modes might be defined where bit values directly correspond to   873 the red, green and blue channels, although this would mostly make sense only   874 for modes with depths greater than the standard 4 bits per pixel, and such   875 modes would require more memory than MODE 2 if they were to have an acceptable   876 resolution.   877    878 Enhancement: Display Suspend   879 ----------------------------   880    881 Especially when writing to the screen memory, it could be beneficial to be   882 able to suspend the ULA's access to the memory, instead producing blank values   883 for all screen pixels until a program is ready to reveal the screen. This is   884 different from palette blanking since with a blank palette, the ULA is still   885 reading screen memory and translating its contents into pixel values that end   886 up being blank.   887    888 This function is reminiscent of a capability of the ZX81, albeit necessary on   889 that hardware to reduce the load on the system CPU which was responsible for   890 producing the video output. By allowing display suspend on the Electron, the   891 performance benefit would be derived from giving the CPU full access to the   892 memory bandwidth.   893    894 The region blanking feature mentioned above could be implemented using this   895 enhancement instead of employing palette blanking for the affected lines of   896 the display.   897    898 Enhancement: Memory Filling   899 ---------------------------   900    901 A capability that could be given to an enhanced ULA is that of permitting the   902 ULA to write to screen memory as well being able to read from it. Although   903 such a capability would probably not be useful in conjunction with the   904 existing read operations when producing a screen display, and insufficient   905 bandwidth would exist to do so in high-bandwidth screen modes anyway, the   906 capability could be offered during a display suspend period (as described   907 above), permitting a more efficient mechanism to rapidly fill memory with a   908 predetermined value.   909    910 This capability could also support block filling, where the limits of the   911 filled memory would be defined by the position and size of a screen area,   912 although this would demand the provision of additional registers in the ULA to   913 retain the details of such areas and additional logic to control the fill   914 operation.   915    916 Enhancement: Region Filling   917 ---------------------------   918    919 An alternative to memory writing might involve indicating regions using   920 additional registers or memory where the ULA fills regions of the screen with   921 content instead of reading from memory. Unlike hardware sprites which should   922 realistically provide varied content, region filling could employ single   923 colours or patterns, and one advantage of doing so would be that the ULA need   924 not access memory at all within a particular region.   925    926 Regions would be defined on a row-by-row basis. Instead of reading memory and   927 blitting a direct representation to the screen, the ULA would read region   928 definitions containing a start column, region width and colour details. There   929 might be a certain number of definitions allowed per row, or the ULA might   930 just traverse an ordered list of such definitions with each one indicating the   931 row, start column, region width and colour details.   932    933 One could even compress this information further by requiring only the row,   934 start column and colour details with each subsequent definition terminating   935 the effect of the previous one. However, one would also need to consider the   936 convenience of preparing such definitions and whether efficient access to   937 definitions for a particular row might be desirable. It might also be   938 desirable to avoid having to prepare definitions for "empty" areas of the   939 screen, effectively making the definition of the screen contents employ   940 run-length encoding and employ only colour plus length information.   941    942 One application of region filling is that of simple 2D and 3D shape rendering.   943 Although it is entirely possible to plot such shapes to the screen and have   944 the ULA blit the memory contents to the screen, such operations consume   945 bandwidth both in the initial plotting and in the final transfer to the   946 screen. Region filling would reduce such bandwidth usage substantially.   947    948 This way of representing screen images would make certain kinds of images   949 unfeasible to represent - consider alternating single pixel values which could   950 easily occur in some character bitmaps - even if an internal queue of regions   951 were to be supported such that the ULA could read ahead and buffer such   952 "bandwidth intensive" areas. Thus, the ULA might be better served providing   953 this feature for certain areas of the display only as some kind of special   954 graphics window.   955    956 Enhancement: Hardware Sprites   957 -----------------------------   958    959 An enhanced ULA might provide hardware sprites, but this would be done in an   960 way that is incompatible with the standard ULA, since no &FE*X locations are   961 available for allocation. To keep the facility simple, hardware sprites would   962 have a standard byte width and height.   963    964 The specification of sprites could involve the reservation of 16 locations   965 (for example, &FE20-F) specifying a fixed number of eight sprites, with each   966 location pair referring to the sprite data. By limiting the ULA to dealing   967 with a fixed number of sprites, the work required inside the ULA would be   968 reduced since it would avoid having to deal with arbitrary numbers of sprites.   969    970 The principal limitation on providing hardware sprites is that of having to   971 obtain sprite data, given that the ULA is usually required to retrieve screen   972 data, and given the lack of memory bandwidth available to retrieve sprite data   973 (particularly from multiple sprites supposedly at the same position) and   974 screen data simultaneously. Although the ULA could potentially read sprite   975 data and screen data in alternate memory accesses in screen modes where the   976 bandwidth is not already fully utilised, this would result in a degradation of   977 performance.   978    979 Enhancement: Additional Screen Mode Configurations   980 --------------------------------------------------   981    982 Alternative screen mode configurations could be supported. The ULA has to   983 produce 640 pixel values across the screen, with pixel doubling or quadrupling   984 employed to fill the screen width:   985    986   Screen width      Columns     Scaling     Depth       Bytes   987   ------------      -------     -------     -----       -----   988   640               80          x1          1           80   989   320               40          x2          1, 2        40, 80   990   160               20          x4          2, 4        40, 80   991    992 It must also use at most 80 byte-sized memory accesses to provide the   993 information for the display. Given that characters must occupy an 8x8 pixel   994 array, if a configuration featuring anything other than 20, 40 or 80 character   995 columns is to be supported, compromises must be made such as the introduction   996 of blank pixels either between characters (such as occurs between rows in MODE   997 3 and 6) or at the end of a scanline (such as occurs at the end of the frame   998 in MODE 3 and 6). Consider the following configuration:   999   1000   Screen width      Columns     Scaling     Depth       Bytes       Blank  1001   ------------      -------     -------     -----       ------      -----  1002   208               26          x3          1, 2        26, 52      16  1003   1004 Here, if the ULA can triple pixels, a 26 column mode with either 2 or 4  1005 colours could be provided, with 16 blank pixel values (out of a total of 640)  1006 generated either at the start or end (or split between the start and end) of  1007 each scanline.  1008   1009 Enhancement: Character Attributes  1010 ---------------------------------  1011   1012 The BBC Micro MODE 7 employs something resembling character attributes to  1013 support teletext displays, but depends on circuitry providing a character  1014 generator. The ZX Spectrum, on the other hand, provides character attributes  1015 as a means of colouring bitmapped graphics. Although such a feature is very  1016 limiting as the sole means of providing multicolour graphics, in situations  1017 where the choice is between low resolution multicolour graphics or high  1018 resolution monochrome graphics, character attributes provide a potentially  1019 useful compromise.  1020   1021 For each byte read, the ULA must deliver 8 pixel values (out of a total of  1022 640) to the video output, doing so by either emptying its pixel buffer on a  1023 pixel per cycle basis, or by multiplying pixels and thus holding them for more  1024 than one cycle. For example for a screen mode having 640 pixels in width:  1025   1026   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  1027   Reads:    B                               B  1028   Pixels:   0   1   2   3   4   5   6   7   0   1   2   3   4   5   6   7  1029   1030 And for a screen mode having 320 pixels in width:  1031   1032   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  1033   Reads:    B  1034   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7  1035   1036 However, in modes where less than 80 bytes are required to generate the pixel  1037 values, an enhanced ULA might be able to read additional bytes between those  1038 providing the bitmapped graphics data:  1039   1040   Cycle:    0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  1041   Reads:    B                               A  1042   Pixels:   0   0   1   1   2   2   3   3   4   4   5   5   6   6   7   7  1043   1044 These additional bytes could provide colour information for the bitmapped data  1045 in the following character column (of 8 pixels). Since it would be desirable  1046 to apply attribute data to the first column, the initial 8 cycles might be  1047 configured to not produce pixel values.  1048   1049 For an entire character, attribute data need only be read for the first row of  1050 pixels for a character. The subsequent rows would have attribute information  1051 applied to them, although this would require the attribute data to be stored  1052 in some kind of buffer. Thus, the following access pattern would be observed:  1053   1054   Reads:    A B _ B _ B _ B _ B _ B _ B _ B ...  1055   1056 In modes 3 and 6, the blank display lines could be used to retrieve attribute  1057 data:  1058   1059   Reads (blank):     A _ A _ A _ A _ A _ A _ A _ A _ ...  1060   Reads (active):    B _ B _ B _ B _ B _ B _ B _ B _ ...  1061   Reads (active):    B _ B _ B _ B _ B _ B _ B _ B _ ...  1062                      ...  1063   1064 See below for a discussion of using this for character data as well.  1065   1066 A whole byte used for colour information for a whole character would result in  1067 a choice of 256 colours, and this might be somewhat excessive. By only reading  1068 attribute bytes at every other opportunity, a choice of 16 colours could be  1069 applied individually to two characters.  1070   1071   Cycle:    0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1  1072   Reads:    B               A               B               -  1073   Pixels:   0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7  1074   1075 Further reductions in attribute data access, offering 4 colours for every  1076 character in a four character block, for example, might also be worth  1077 considering.  1078   1079 Consider the following configurations for screen modes with a colour depth of  1080 1 bit per pixel for bitmap information:  1081   1082   Screen width  Columns  Scaling  Bytes (B)  Bytes (A)  Colours  Screen start  1083   ------------  -------  -------  ---------  ---------  -------  ------------  1084   320           40       x2       40         40         256      &5300  1085   320           40       x2       40         20         16       &5580 -> &5500  1086   320           40       x2       40         10         4        &56C0 -> &5600  1087   208           26       x3       26         26         256      &62C0 -> &6200  1088   208           26       x3       26         13         16       &6460 -> &6400  1089   1090 Enhancement: Text-Only Modes using Character and Attribute Data  1091 ---------------------------------------------------------------  1092   1093 In modes 3 and 6, the blank display lines could be used to retrieve character  1094 and attribute data instead of trying to insert it between bitmap data accesses,  1095 but this data would then need to be retained:  1096   1097   Reads:    A C A C A C A C A C A C A C A C ...  1098   Reads:    B _ B _ B _ B _ B _ B _ B _ B _ ...  1099   1100 Only attribute (A) and character (C) reads would require screen memory  1101 storage. Bitmap data reads (B) would involve either accesses to memory to  1102 obtain character definition details or could, at the cost of special storage  1103 in the ULA, involve accesses within the ULA that would then free up the RAM.  1104 However, the CPU would not benefit from having any extra access slots due to  1105 the limitations of the RAM access mechanism.  1106   1107 A scheme without caching might be possible. The same line of memory addresses  1108 might be visited over and over again for eight display lines, with an index  1109 into the bitmap data being incremented from zero to seven. The access patterns  1110 would look like this:  1111   1112   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 0)  1113   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 1)  1114   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 2)  1115   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 3)  1116   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 4)  1117   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 5)  1118   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 6)  1119   Reads:    C B C B C B C B C B C B C B C B ... (generate data from index 7)  1120   1121 The bandwidth requirements would be the sum of the accesses to read the  1122 character values (repeatedly) and those to read the bitmap data to reproduce  1123 the characters on screen.  1124   1125 Enhancement: MODE 7 Emulation using Character Attributes  1126 --------------------------------------------------------  1127   1128 If the scheme of applying attributes to character regions were employed to  1129 emulate MODE 7, in conjunction with the MODE 6 display technique, the  1130 following configuration would be required:  1131   1132   Screen width  Columns  Rows  Bytes (B)  Bytes (A)  Colours  Screen start  1133   ------------  -------  ----  ---------  ---------  -------  ------------  1134   320           40       25    40         20         16       &5ECC -> &5E00  1135   320           40       25    40         10         4        &5FC6 -> &5F00  1136   1137 Although this requires much more memory than MODE 7 (8500 bytes versus MODE  1138 7's 1000 bytes), it does not need much more memory than MODE 6, and it would  1139 at least make a limited 40-column multicolour mode available as a substitute  1140 for MODE 7.  1141   1142 Using the text-only enhancement with caching of data or with repeated reads of  1143 the same character data line for eight display lines, the storage requirements  1144 would be diminished substantially:  1145   1146   Screen width  Columns  Rows  Bytes (C)  Bytes (A)  Colours  Screen start  1147   ------------  -------  ----  ---------  ---------  -------  ------------  1148   320           40       25    40         20         16       &7A94 -> &7A00  1149   320           40       25    40         10         4        &7B1E -> &7B00  1150   320           40       25    40         5          2        &7B9B -> &7B00  1151   320           40       25    40         0          (2)      &7C18 -> &7C00  1152   640           80       25    80         40         16       &7448 -> &7400  1153   640           80       25    80         20         4        &763C -> &7600  1154   640           80       25    80         10         2        &7736 -> &7700  1155   640           80       25    80         0          (2)      &7830 -> &7800  1156   1157 Note that the colours describe the locally defined attributes for each  1158 character. When no attribute information is provided, the colours are defined  1159 globally.  1160   1161 Enhancement: Compressed Character Data  1162 --------------------------------------  1163   1164 Another observation about text-only modes is that they only need to store a  1165 restricted set of bitmapped data values. Encoding this set of values in a  1166 smaller unit of storage than a byte could possibly help to reduce the amount  1167 of storage and bandwidth required to reproduce the characters on the display.  1168   1169 Enhancement: High Resolution Graphics  1170 -------------------------------------  1171   1172 Screen modes with higher resolutions and larger colour depths might be  1173 possible, but this would in most cases involve the allocation of more screen  1174 memory, and the ULA would probably then be obliged to page in such memory for  1175 the CPU to be able to sensibly access it all.  1176   1177 Enhancement: Genlock Support  1178 ----------------------------  1179   1180 The ULA generates a video signal in conjunction with circuitry producing the  1181 output features necessary for the correct display of the screen image.  1182 However, it appears that the ULA drives the video synchronisation mechanism  1183 instead of reacting to an existing signal. Genlock support might be possible  1184 if the ULA were made to be responsive to such external signals, resetting its  1185 address generators upon receiving synchronisation events.  1186   1187 Enhancement: Improved Sound  1188 ---------------------------  1189   1190 The standard ULA reserves &FE*6 for sound generation and cassette input/output  1191 (with bits 1 and 2 of &FE*7 being used to select either sound generation or  1192 cassette I/O), thus making it impossible to support multiple channels within  1193 the given framework. The BBC Micro ULA employs &FE40-&FE4F for sound control,  1194 and an enhanced ULA could adopt this interface.  1195   1196 The BBC Micro uses the SN76489 chip to produce sound, and the entire  1197 functionality of this chip could be emulated for enhanced sound, with a subset  1198 of the functionality exposed via the &FE*6 interface.  1199   1200 See: http://en.wikipedia.org/wiki/Texas_Instruments_SN76489  1201 See: http://www.smspower.org/Development/SN76489  1202   1203 Enhancement: Waveform Upload  1204 ----------------------------  1205   1206 As with a hardware sprite function, waveforms could be uploaded or referenced  1207 using locations as registers referencing memory regions.  1208   1209 Enhancement: Sound Input/Output  1210 -------------------------------  1211   1212 Since the ULA already controls audio input/output for cassette-based data, it  1213 would have been interesting to entertain the idea of sampling and output of  1214 sounds through the cassette interface. However, a significant amount of  1215 circuitry is employed to process the input signal for use by the ULA and to  1216 process the output signal for recording.  1217   1218 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw_03.htm#3.11  1219   1220 Enhancement: BBC ULA Compatibility  1221 ----------------------------------  1222   1223 Although some new ULA functions could be defined in a way that is also  1224 compatible with the BBC Micro, the BBC ULA is itself incompatible with the  1225 Electron ULA: &FE00-7 is reserved for the video controller in the BBC memory  1226 map, but controls various functions specific to the 6845 video controller;  1227 &FE08-F is reserved for the serial controller. It therefore becomes possible  1228 to disregard compatibility where compatibility is already disregarded for a  1229 particular area of functionality.  1230   1231 &FE20-F maps to video ULA functionality on the BBC Micro which provides  1232 control over the palette (using address &FE21, compared to &FE07-F on the  1233 Electron) and other system-specific functions. Since the location usage is  1234 generally incompatible, this region could be reused for other purposes.  1235   1236 Enhancement: Increased RAM, ULA and CPU Performance  1237 ---------------------------------------------------  1238   1239 More modern implementations of the hardware might feature faster RAM coupled  1240 with an increased ULA clock frequency in order to increase the bandwidth  1241 available to the ULA and to the CPU in situations where the ULA is not needed  1242 to perform work. A ULA employing a 32MHz clock would be able to complete the  1243 retrieval of a byte from RAM in only 250ns and thus be able to enable the CPU  1244 to access the RAM for the following 250ns even in display modes requiring the  1245 retrieval of a byte for the display every 500ns. The CPU could, subject to  1246 timing issues, run at 2MHz even in MODE 0, 1 and 2.  1247   1248 A scheme such as that described above would have a similar effect to the  1249 scheme employed in the BBC Micro, although the latter made use of RAM with a  1250 wider bandwidth in order to complete memory transfers within 250ns and thus  1251 permit the CPU to run continuously at 2MHz.  1252   1253 Higher bandwidth could potentially be used to implement exotic features such  1254 as RAM-resident hardware sprites or indeed any feature demanding RAM access  1255 concurrent with the production of the display image.  1256   1257 Enhancement: Multiple CPU Stacks and Zero Pages  1258 -----------------------------------------------  1259   1260 The 6502 maintains a stack for subroutine calls and register storage in page  1261 &01. Although the stack register can be manipulated using the TSX and TXS  1262 instructions, thereby permitting the maintenance of multiple stack regions and  1263 thus the potential coexistence of multiple programs each using a separate  1264 region, only programs that make little use of the stack (perhaps avoiding  1265 deeply-nested subroutine invocations and significant register storage) would  1266 be able to coexist without overwriting each other's stacks.  1267   1268 One way that this issue could be alleviated would involve the provision of a  1269 facility to redirect accesses to page &01 to other areas of memory. The ULA  1270 would provide a register that defines a physical page for the use of the CPU's  1271 "logical" page &01, and upon any access to page &01 by the CPU, the ULA would  1272 change the asserted address lines to redirect the access to the appropriate  1273 physical region.  1274   1275 By providing an 8-bit register, mapping to the most significant byte (MSB) of  1276 a 16-bit address, the ULA could then replace any MSB equal to &01 with the  1277 register value before the access is made. Where multiple programs coexist,  1278 upon switching programs, the register would be updated to point the ULA to the  1279 appropriate stack location, thus providing a simple memory management unit  1280 (MMU) capability.  1281   1282 In a similar fashion, zero page accesses could also be redirected so that code  1283 could run from sideways RAM and have zero page operations redirected to "upper  1284 memory" - for example, to page &BE (with stack accesses redirected to page  1285 &BF, perhaps) - thereby permitting most CPU operations to occur without  1286 inadvertent accesses to "lower memory" (the RAM) which would risk stalling the  1287 CPU as it contends with the ULA for memory access.  1288   1289 Such facilities could also be provided by a separate circuit between the CPU  1290 and ULA in a fashion similar to that employed by a "turbo" board, but unlike  1291 such boards, no additional RAM would be provided: all memory accesses would  1292 occur as normal through the ULA, albeit redirected when configured  1293 appropriately.  1294   1295 ULA Pin Functions  1296 -----------------  1297   1298 The functions of the ULA pins are described in the Electron Service Manual. Of  1299 interest to video processing are the following:  1300   1301   CSYNC (low during horizontal or vertical synchronisation periods, high  1302          otherwise)  1303   1304   HS (low during horizontal synchronisation periods, high otherwise)  1305   1306   RED, GREEN, BLUE (pixel colour outputs)  1307   1308   CLOCK IN (a 16MHz clock input, 4V peak to peak)  1309   1310   PHI OUT (a 1MHz, 2MHz and stopped clock signal for the CPU)  1311   1312 More general memory access pins:  1313   1314   RAM0...RAM3 (data lines to/from the RAM)  1315   1316   RA0...RA7 (address lines for sending both row and column addresses to the RAM)  1317   1318   RAS (row address strobe setting the row address on a negative edge - see the  1319        timing notes)  1320   1321   CAS (column address strobe setting the column address on a negative edge -  1322        see the timing notes)  1323   1324   WE (sets write enable with logic 0, read with logic 1)  1325   1326   ROM (select data access from ROM)  1327   1328 CPU-oriented memory access pins:  1329   1330   A0...A15 (CPU address lines)  1331   1332   PD0...PD7 (CPU data lines)  1333   1334   R/W (indicates CPU write with logic 0, CPU read with logic 1)  1335   1336 Interrupt-related pins:  1337   1338   NMI (CPU request for uninterrupted 1MHz access to memory)  1339   1340   IRQ (signal event to CPU)  1341   1342   POR (power-on reset, resetting the ULA on a positive edge and asserting the  1343        CPU's RST pin)  1344   1345   RST (master reset for the CPU signalled on power-up and by the Break key)  1346   1347 Keyboard-related pins:  1348   1349   KBD0...KBD3 (keyboard inputs)  1350   1351   CAPS LOCK (control status LED)  1352   1353 Sound-related pins:  1354   1355   SOUND O/P (sound output using internal oscillator)  1356   1357 Cassette-related pins:  1358   1359   CAS IN (cassette circuit input, between 0.5V to 2V peak to peak)  1360   1361   CAS OUT (pseudo-sinusoidal output, 1.8V peak to peak)  1362   1363   CAS RC (detect high tone)  1364   1365   CAS MO (motor relay output)  1366   1367   ?13 IN (~1200 baud clock input)  1368   1369 ULA Socket  1370 ----------  1371   1372 The socket used for the ULA is a 3M/TexTool 268-5400 68-pin socket.  1373   1374 References  1375 ----------  1376   1377 See: http://bbc.nvg.org/doc/A%20Hardware%20Guide%20for%20the%20BBC%20Microcomputer/bbc_hw.htm  1378   1379 About this Document  1380 -------------------  1381   1382 The most recent version of this document and accompanying distribution should  1383 be available from the following location:  1384   1385 http://hgweb.boddie.org.uk/ULA  1386   1387 Copyright and licence information can be found in the docs directory of this  1388 distribution - see docs/COPYING.txt for more information.