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Added Acorn dealer pricing note. |
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Added more RAM pricing data. |
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Added a note about 4MHz CPU/ULA memory access interleaving. |
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Added character generator support enhancement. |
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Expanded mode property relationship descriptions; introduced tables. |
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Added notes about mode numbering and selection in the ULA, suggesting an |
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Added more component pricing details and discussion. |
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Added notes about memory pricing and other machines using the 4164. |
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Added a note about the CPU performance limitations of suspending ULA RAM access. |
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Added notes on two-bytes-per-cycle ULA accesses and related considerations. |
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Added benchmark observations and a table of standard bandwidth characteristics. |
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Added clarifications about the use of 8MHz cycles with an 8-bit memory channel. |
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Added notes on 4164 RAM costs referencing historical remarks. |
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Added more remarks, particularly regarding direct CPU access to RAM. |
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Added remarks on 8-bit wide RAM access and possible 8MHz ULA frequency. |
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Added some memory bandwidth and architecture notes. |
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Added a note about keyboard access timings. |
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Added some notes about RAM access and the limitations applying to the CPU. |
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Made clarification about 1MHz RAM access, added 2MHz bandwidth figure. |
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Added some notes about video expansions and ULA simplification. |
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Noted that the ULA could re-read the character values and just increment an |
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Added notes about text-only modes, plus character and attribute value retrieval |
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Added CPU clock input and output notes. |
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Added a note about the CPU clock phases. |
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Added explicit reason for 2MHz RAM access not being feasible. |
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Introduced explicit next_frame calls after updating the screen start address. |
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Attempted to introduce hardware description language limitations, restructuring |
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Introduced a separate state-updating method and reordered methods. |
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Moved pixel generation to after the state update in the negative edge handler. |
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Moved video signalling into the negative edge handler in order to consolidate |
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Added notes about RAM access limitations preventing 2MHz RAM access by the CPU. |
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Removed the width instance attribute. |
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Moved address preparation onto negative edges and data acquisition onto positive |
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Shifted the timing states so that cycle 0 is aligned with the positive edge of |
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Refined and expanded the RAM access timings, moving data transfers to the |
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Renamed address to pixel_address. |
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Added initial CPU abstraction support together with read/write selection and |
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Made the next_vertical control-flow more hierarchical. |
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Introduced positive and negative signal transition update methods in order to |
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Tidied, introducing a write_pixels function, removing PIXEL_POSITIONS. |
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Fixed and tidied up pixel production, employing the general state counter for |
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Fixed the timing of pixel data decoding. Made the pixel data a plain integer. |
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Initialise the palette as red/green/blue triples. |
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Replaced the pixel buffer with translated byte data and a function converting |
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Changed the processing of pixel data and added remarks about pixel layout. |
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Replaced row spacing variables with row height and row offset variables. |
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Renamed reset methods and tidied slightly. |
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Separated address updating from the NMI-dependent RAM access condition. |
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Use the horizontal position counter by itself to manage the pixel buffer. |
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Refined video timings according to measurements and a review of the documents. |
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Introduced a pixel position counter, eliminating the horizontal position counter |
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Separated out the screen layout section and described a column-oriented layout. |
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Updated Amstrad CPC-related notes concerning extra colour information. |
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Added a note about redirecting zero page accesses as well as stack accesses. |
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Added a textual MODE 1 enhancement plus remarks about display interrupts. |
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Added 625-line, 312/313 scanline notes. |
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Added a note about the 2MHz RAM access enhancement. |
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Added RAM access corrections related to CPU activity plus bandwidth figures. |
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Added multiple CPU stack "MMU" enhancement. |
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Added region blanking and display suspend notes. |
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