# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1466549514 -7200
# Node ID 2a568a84bbafa3cf3df9522f1dc20f2db1f190ea
# Parent  d22e09bd1f7e424bb7f1d2410a563e694209ff45
Moved video signalling into the negative edge handler in order to consolidate
updates to the horizontal and vertical pixel positions.

diff -r d22e09bd1f7e -r 2a568a84bbaf ula.py
--- a/ula.py	Tue Jun 21 23:22:33 2016 +0200
+++ b/ula.py	Wed Jun 22 00:51:54 2016 +0200
@@ -335,44 +335,9 @@
 
         "Update the state of the ULA for each clock cycle."
 
-        self.posedge_video()
         self.posedge_ram()
         self.posedge_pixel()
 
-    def posedge_video(self):
-
-        "Video signalling."
-
-        # Detect the end of the scanline.
-
-        if self.x == MAX_SCANPOS:
-            self.next_vertical()
-
-        # Detect the end of the frame.
-
-        if self.y == MAX_SCANLINE:
-            self.next_frame()
-
-        # Detect any sync conditions.
-
-        if self.x == 0:
-            self.hsync()
-            if self.y == 0:
-                self.vsync()
-                self.irq_vsync = 0
-            elif self.y == MAX_PIXELLINE:
-                self.irq_vsync = 1
-
-        # Detect the end of hsync.
-
-        elif self.x == MAX_HSYNC:
-            self.hsync(1)
-
-        # Detect the end of vsync.
-
-        elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2:
-            self.vsync(1)
-
     def posedge_ram(self):
 
         """
@@ -469,7 +434,50 @@
     def negedge(self):
 
         """
-        Update the state of the device.
+        Update the state of the device on the negative edge of each clock cycle.
+        """
+
+        self.negedge_video()
+        self.negedge_ram()
+
+    def negedge_video(self):
+
+        "Video signalling."
+
+        # Detect the end of the scanline.
+
+        if self.x == MAX_SCANPOS:
+            self.next_vertical()
+
+        # Detect the end of the frame.
+
+        if self.y == MAX_SCANLINE:
+            self.next_frame()
+
+        # Detect any sync conditions.
+
+        if self.x == 0:
+            self.hsync()
+            if self.y == 0:
+                self.vsync()
+                self.irq_vsync = 0
+            elif self.y == MAX_PIXELLINE:
+                self.irq_vsync = 1
+
+        # Detect the end of hsync.
+
+        elif self.x == MAX_HSYNC:
+            self.hsync(1)
+
+        # Detect the end of vsync.
+
+        elif self.y == MAX_CSYNC and self.x == MAX_SCANPOS / 2:
+            self.vsync(1)
+
+    def negedge_ram(self):
+
+        """
+        Prepare addresses and pixel data.
 
         States handled: * * * _ _ * _ *
         """