# HG changeset patch # User Paul Boddie # Date 1550969730 -3600 # Node ID 46bcedba4e276aa1ef6a792e2f94a3f38f013bed # Parent bb63d97d265e928978bbbc1b252dd9f5be2acb85 Made clarification about 1MHz RAM access, added 2MHz bandwidth figure. Fixed service manual link. diff -r bb63d97d265e -r 46bcedba4e27 ULA.txt --- a/ULA.txt Fri Feb 22 16:05:35 2019 +0100 +++ b/ULA.txt Sun Feb 24 01:55:30 2019 +0100 @@ -42,11 +42,12 @@ of the 2MHz clock to complete each access operation. Since the CPU and ULA have to take turns in accessing the RAM in MODE 4, 5 and 6, the CPU must effectively run at 1MHz (since every other 500ns period involves the ULA -accessing RAM). The CPU is driven by an external clock (IC8) whose 16MHz -frequency is divided by the ULA (IC1) depending on the screen mode in use. +accessing RAM) during transfers of screen data. -Each 16MHz cycle is approximately 62.5ns. To access the memory, the following -patterns corresponding to 16MHz cycles are required: +The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided +by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is +approximately 62.5ns. To access the memory, the following patterns +corresponding to 16MHz cycles are required: Time (ns): 0-------------- 500------------- ... 2 MHz cycle: 0 1 ... @@ -116,7 +117,7 @@ See: Acorn Electron Advanced User Guide See: Acorn Electron Service Manual - http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf + http://chrisacorns.computinghistory.org.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438 @@ -622,6 +623,9 @@ MODE 4, 5 19968 bytes 29696 bytes MODE 6 19968 bytes 32256 bytes +(Here, the uncontended 2MHz bandwidth for a display period would be 39936 +bytes, being 128 cycles per line over 312 lines.) + With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth because all access opportunities to RAM are doubled. Meanwhile, in the other modes, some CPU accesses occur alongside ULA accesses and thus cannot be