# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1330294355 -3600
# Node ID 4adc54716f92634f1986d3977e30b6c5701f7196
# Parent  726152e626d558fd3336c7ecdc2f0a46018cc8d6
Added notes on interrupt generation and ROM paging.

diff -r 726152e626d5 -r 4adc54716f92 ULA.txt
--- a/ULA.txt	Sun Feb 26 23:11:44 2012 +0100
+++ b/ULA.txt	Sun Feb 26 23:12:35 2012 +0100
@@ -120,6 +120,42 @@
 See: Acorn Electron Service Manual
      http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
 
+Interrupts
+----------
+
+The ULA generates IRQs (maskable interrupts) according to certain conditions
+and these conditions are controlled by location &FE00:
+
+  * Vertical sync (bottom of displayed screen)
+  * 50MHz real time clock
+  * Transmit data empty
+  * Receive data full
+  * High tone detect
+
+The ULA is also used to clear interrupt conditions through location &FE05. Of
+particular significance is bit 7, which must be set if an NMI (non-maskable
+interrupt) has occurred and has thus suspended ULA access to memory, restoring
+the normal function of the ULA.
+
+ROM Paging
+----------
+
+Accessing different ROMs involves bits 0 to 3 of &FE05. Some special ROM
+mappings exist:
+
+   8    keyboard
+   9    keyboard (duplicate)
+  10    BASIC ROM
+  11    BASIC ROM (duplicate)
+
+Paging in a ROM involves the following procedure:
+
+ 1. Assert ROM page enable (bit 3) together with a ROM number n in bits 0 to
+    2, corresponding to ROM number 8+n, such that one of ROMs 12 to 15 is
+    selected.
+ 2. Where a ROM numbered from 0 to 7 is to be selected, set bit 3 to zero
+    whilst writing the desired ROM number n in bits 0 to 2.
+
 Shadow/Expanded Memory
 ----------------------
 
diff -r 726152e626d5 -r 4adc54716f92 ula.py
--- a/ula.py	Sun Feb 26 23:11:44 2012 +0100
+++ b/ula.py	Sun Feb 26 23:12:35 2012 +0100
@@ -152,6 +152,11 @@
 
         "Reset the ULA."
 
+        # General state.
+
+        self.nmi = 0            # no NMI asserted initially
+        self.irq_vsync = 0      # no IRQ asserted initially
+
         # Internal state.
 
         self.cycle = 0          # counter within each 2MHz period
@@ -302,7 +307,7 @@
 
         # Clock management.
 
-        access_ram = self.access == 0 and self.read_pixels() and not self.ssub
+        access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
 
         # Set row address (for ULA access only).
 
@@ -411,6 +416,9 @@
             self.hsync()
             if self.y == 0:
                 self.vsync()
+                self.irq_vsync = 0
+            elif self.y == MAX_PIXELLINE:
+                self.irq_vsync = 1
 
         # Detect the end of hsync.