# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1466345937 -7200
# Node ID 5cd431fd023356f68cc319c1077aab24bd46c9e3
# Parent  bface8225ae4ece6093f7d2e448688cd6a0963f9
Separated address updating from the NMI-dependent RAM access condition.

diff -r bface8225ae4 -r 5cd431fd0233 ula.py
--- a/ula.py	Sun Jun 19 16:15:39 2016 +0200
+++ b/ula.py	Sun Jun 19 16:18:57 2016 +0200
@@ -363,7 +363,8 @@
 
         # Clock management.
 
-        access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
+        would_access_ram = self.access == 0 and self.read_pixels() and not self.ssub
+        access_ram = not self.nmi and would_access_ram
 
         # Set row address (for ULA access only).
 
@@ -448,13 +449,14 @@
             if access_ram:
                 self.data = self.data | self.ram.data
                 self.have_pixels = 1
+            else:
+                self.cpu_transfer_low()
 
-                # Advance to the next column.
+            # Advance to the next column even if an NMI is asserted.
 
+            if would_access_ram:
                 self.address += LINES_PER_ROW
                 self.wrap_address()
-            else:
-                self.cpu_transfer_low()
 
         # Reset addresses.