# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1472943580 -7200
# Node ID 65b890e3e7f68e65612319b8eefe602cceaeed74
# Parent  19850e9d0183fa6de054844c4788f30ddc236165
Added explicit reason for 2MHz RAM access not being feasible.

diff -r 19850e9d0183 -r 65b890e3e7f6 ULA.txt
--- a/ULA.txt	Thu Jun 23 23:02:23 2016 +0200
+++ b/ULA.txt	Sun Sep 04 00:59:40 2016 +0200
@@ -601,7 +601,8 @@
 doubled, but the CPU bandwidth increase is still significant.
 
 Unfortunately, the mechanism for accessing the RAM is too slow to provide data
-within the time constraints of 2MHz operation.
+within the time constraints of 2MHz operation. There is no time remaining in a
+2MHz cycle for the CPU to receive and process any retrieved data.
 
 Enhancement: Region Blanking
 ----------------------------