# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1554763772 -7200
# Node ID 69f0c87496c6aa31bc9c7c32f24fd652b7eaa868
# Parent  46bcedba4e276aa1ef6a792e2f94a3f38f013bed
Added some notes about RAM access and the limitations applying to the CPU.

diff -r 46bcedba4e27 -r 69f0c87496c6 ULA.txt
--- a/ULA.txt	Sun Feb 24 01:55:30 2019 +0100
+++ b/ULA.txt	Tue Apr 09 00:49:32 2019 +0200
@@ -4,15 +4,17 @@
 Principal Design and Feature Constraints
 ----------------------------------------
 
-The features of the ULA are limited by the amount of time and resources that
-can be allocated to each activity necessary to support such features given the
-fundamental obligations of the unit. Maintaining a screen display based on the
-contents of RAM itself requires the ULA to have exclusive access to such
-hardware resources for a significant period of time. Whilst other elements of
-the ULA can in principle run in parallel with this activity, they cannot also
-access the RAM. Consequently, other features that might use the RAM must
-accept a reduced allocation of that resource in comparison to a hypothetical
-architecture where concurrent RAM access is possible.
+The features of the ULA are limited in sophistication by the amount of time
+and resources that can be allocated to each activity supporting the
+fundamental features and obligations of the unit. Maintaining a screen display
+based on the contents of RAM itself requires the ULA to have exclusive access
+to various hardware resources for a significant period of time.
+
+Whilst other elements of the ULA can in principle run in parallel with the
+display refresh activity, they cannot also access the RAM at the same time.
+Consequently, other features that might use the RAM must accept a reduced
+allocation of that resource in comparison to a hypothetical architecture where
+concurrent RAM access is possible at all times.
 
 Thus, the principal constraint for many features is bandwidth. The duration of
 access to hardware resources is one aspect of this; the rate at which such
@@ -22,6 +24,20 @@
 for anything other than the production of pixel output during the active
 scanline periods.
 
+Another constraint is imposed by the method of RAM access provided by the ULA.
+The ULA is able to access RAM by fetching 4 bits at a time and thus managing
+to transfer 8 bits within a single 2MHz cycle, this being sufficient to
+provide display data for the most demanding screen modes. However, this
+mechanism's timing requirements are beyond the capabilities of the CPU when
+running at 2MHz.
+
+Consequently, the CPU will only ever be able to access RAM via the ULA at
+1MHz, even when the ULA is not accessing the RAM. Fortunately, when needing to
+refresh the display, the ULA is still able to make use of the idle part of
+each 1MHz cycle (or, rather, the idle 2MHz cycle unused by the CPU) to itself
+access the RAM at a rate of 1 byte per 1MHz cycle (or 1 byte every other 2MHz
+cycle), thus supporting the less demanding screen modes.
+
 Timing
 ------