# HG changeset patch # User Paul Boddie # Date 1490993455 -7200 # Node ID 723b5ffe7caa9b33938a29ad0b56785a701c560a # Parent d998a098edb629ff9f33f8ea00bb0b29cbdbcc88 Added CPU clock input and output notes. diff -r d998a098edb6 -r 723b5ffe7caa ULA.txt --- a/ULA.txt Mon Nov 14 18:18:37 2016 +0100 +++ b/ULA.txt Fri Mar 31 22:50:55 2017 +0200 @@ -123,13 +123,29 @@ CPU Clock Notes --------------- +"The 6502 receives an external square-wave clock input signal on pin 37, which +is usually labeled PHI0. [...] This clock input is processed within the 6502 +to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2 +is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been +through two inverters and a push-pull amplifier. The same network of +transistors within the 6502 which generates PHI2 is also tied to PHI1, and +generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made +available to external devices is so that they know when they can access the +CPU. When PHI1 is high, this means that external devices can read from the +address bus or data bus; when PHI2 is high, this means that external devices +can write to the data bus." + +See: http://lateblt.livejournal.com/88105.html + "The 6502 has a synchronous memory bus where the master clock is divided into two phases (Phase 1 and Phase 2). The address is always generated during Phase 1 and all memory accesses take place during Phase 2." -Thus, the inverse of PHI OUT provides the other phase of the clock. +See: http://www.jmargolin.com/vgens/vgens.htm -See: http://www.jmargolin.com/vgens/vgens.htm +Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During +Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means +when PHI1 is high. Bandwidth Figures -----------------