# HG changeset patch # User Paul Boddie # Date 1665876426 -7200 # Node ID 796798b4d18a0e6ddf103ec31ca80496d57b1e83 # Parent 4f4cad6abd6dad33742cf6788b197929396a5ca6 Refined the address timing details slightly. diff -r 4f4cad6abd6d -r 796798b4d18a ULA.txt --- a/ULA.txt Fri Oct 14 17:01:47 2022 +0200 +++ b/ULA.txt Sun Oct 16 01:27:06 2022 +0200 @@ -61,7 +61,7 @@ accessing RAM) during transfers of screen data. The CPU is driven by an external clock (IC8) whose 16MHz frequency is divided -by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is +by the ULA (IC1) depending on the screen mode in use. Each 16MHz cycle is approximately 62.5ns. To access the memory, the following patterns corresponding to 16MHz cycles are required: @@ -77,7 +77,7 @@ ~RAS ops: 1 0 1 0 ... ~CAS ops: 1 0 1 0 1 0 1 0 ... - Address ops: a b c a b c ... + Address ops: a.b. c. a.b. c. ... Data ops: s f s f ... ~WE: ......W ... @@ -98,8 +98,10 @@ respectively), and "C" indicates the second column address being latched into the RAM. Presumably, the first and second half-bytes can be read at "F" and "S" respectively, and the row and column addresses must be made available at -"a" and "b" (and "c") respectively at the latest. Data can be read at "f" and -"s" for the first and second half-bytes respectively. +"a" and "b" (and "c") respectively at the latest. The TM4164EC4 datasheet +suggests that the addresses can be made available as the ~RAS and ~CAS levels +are brought low. Data can be read at "f" and "s" for the first and second +half-bytes respectively. For the CPU, "L" indicates the point at which an address is taken from the CPU address bus, on a negative edge of PHI OUT, with "D" being the point at which