# HG changeset patch # User Paul Boddie # Date 1466201000 -7200 # Node ID ac90d199ac33897a8852ce6f62830297e74ecdc4 # Parent b1f2c3de8b1526f4d2ba4a6de88ced78a1091e5f Refined video timings according to measurements and a review of the documents. diff -r b1f2c3de8b15 -r ac90d199ac33 ULA.txt --- a/ULA.txt Fri Jun 17 20:49:30 2016 +0200 +++ b/ULA.txt Sat Jun 18 00:03:20 2016 +0200 @@ -157,14 +157,26 @@ pixel data period start cycle = 16.375µs / 62.5ns = 262 By choosing a number divisible by 8, the RAM access mechanism can be -synchronised with the pixel production. Thus, 264 is a more appropriate start -cycle. +synchronised with the pixel production. Thus, 256 is a more appropriate start +cycle, where the HS (horizontal sync) signal corresponding to the 4µs sync +pulse (or "normal sync" pulse as described by the "PAL TV timing and voltages" +document) occurs at cycle 0. + +To summarise: + + HS signal starts at cycle 0 on each horizontal scanline + HS signal ends approximately 4µs later at cycle 64 + Pixel data starts approximately 12µs later at cycle 256 + +"Re: Electron Memory Contention" provides measurements that appear consistent +with these calculations. The "vertical blanking period", meaning the period before picture information in each field is 25 lines out of 312 (or 313) and thus lasts for 1.6ms. Of this, 2.5 lines occur before the vsync (field sync) which also lasts for 2.5 lines. Thus, the first visible scanline on the first field of a frame occurs -half way through the 23rd scanline period measured from the start of vsync: +half way through the 23rd scanline period measured from the start of vsync +(indicated by "V" in the diagrams below): 10 20 23 Line in frame: 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 @@ -190,8 +202,17 @@ Again, it is likely that pixel data production should only occur on scanlines within a certain period on each frame. The "625/50" document indicates that only a certain region is "safe" to use, suggesting a vertically centred region -with approximately 15 blank lines above and below the picture. Thus, the start -of the picture could be chosen as 38 lines after the start of vsync. +with approximately 15 blank lines above and below the picture. However, the +"PAL TV timing and voltages" document suggests 28 blank lines above and below +the picture. This would centre the 256 lines within the 312 lines of each +field and thus provide a start of picture approximately 5.5 or 5 lines after +the end of the blanking period or 28 or 27.5 lines after the start of vsync. + +To summarise: + + CSYNC signal starts at cycle 0 + CSYNC signal ends approximately 160µs (2.5 lines) later at cycle 2560 + Start of line occurs approximately 1632µs (5.5 lines) later at cycle 28672 See: http://en.wikipedia.org/wiki/PAL See: http://en.wikipedia.org/wiki/Analog_television#Structure_of_a_video_signal @@ -201,6 +222,10 @@ http://www.retroleum.co.uk/electronics-articles/pal-tv-timing-and-voltages/ See: Line Standards http://www.pembers.freeserve.co.uk/World-TV-Standards/Line-Standards.html +See: Horizontal Blanking Interval of 405-, 525-, 625- and 819-Line Standards + http://www.pembers.freeserve.co.uk/World-TV-Standards/HBI.pdf +See: Re: Electron Memory Contention + http://www.stardot.org.uk/forums/viewtopic.php?p=134109#p134109 RAM Integrated Circuits ----------------------- diff -r b1f2c3de8b15 -r ac90d199ac33 ula.py --- a/ula.py Fri Jun 17 20:49:30 2016 +0200 +++ b/ula.py Sat Jun 18 00:03:20 2016 +0200 @@ -3,7 +3,7 @@ """ Acorn Electron ULA simulation. -Copyright (C) 2011, 2012, 2013, 2014 Paul Boddie +Copyright (C) 2011, 2012, 2013, 2014, 2016 Paul Boddie This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software @@ -26,12 +26,12 @@ MAX_WIDTH = 640 # the width of the screen in pixels MAX_CSYNC = 2 # the scanline during which vsync ends -MIN_PIXELLINE = 38 # the first scanline involving pixel generation +MIN_PIXELLINE = 28 # the first scanline involving pixel generation MAX_SCANLINE = 312 # the number of scanlines in each frame MAX_PIXELLINE = MIN_PIXELLINE + MAX_HEIGHT -MAX_HSYNC = 75 # the number of cycles in each hsync period +MAX_HSYNC = 64 # the number of cycles in each hsync period MIN_PIXELPOS = 256 # the first cycle involving pixel generation MAX_SCANPOS = 1024 # the number of cycles in each scanline