# HG changeset patch
# User Paul Boddie <paul@boddie.org.uk>
# Date 1441539687 -7200
# Node ID cabf7421f46120be39509dffef62cf2e81deca43
# Parent  73ec9c2e0c11213000cd8225c4e043fc6c743930
Added RAM access corrections related to CPU activity plus bandwidth figures.
Consequently, an inevitable enhancement is proposed to remedy the situation.

diff -r 73ec9c2e0c11 -r cabf7421f461 ULA.txt
--- a/ULA.txt	Tue Aug 25 22:57:24 2015 +0200
+++ b/ULA.txt	Sun Sep 06 13:41:27 2015 +0200
@@ -70,10 +70,60 @@
 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
 "page mode" provides the appropriate behaviour for that particular product.
 
+The CPU, when accessing the RAM alone, apparently does not make use of the
+vacated "slot" that the ULA would otherwise use (when interleaving accesses in
+MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
+accessing ROM (and potentially sideways RAM).
+
 See: Acorn Electron Advanced User Guide
 See: Acorn Electron Service Manual
      http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
+See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
+
+Bandwidth Figures
+-----------------
+
+Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
+total lines, with 80 cycles occurring in the active periods of display
+scanlines, the following bandwidth calculations can be performed:
+
+Total theoretical maximum:
+       128 cycles * 312 lines
+     = 39936 bytes
+
+MODE 0, 1, 2:
+ULA:    80 cycles * 256 lines
+     = 20480 bytes
+CPU:    48 cycles / 2 * 256 lines
+     + 128 cycles / 2 * (312 - 256) lines
+     = 9728 bytes
+
+MODE 3:
+ULA:    80 cycles * 24 rows * 8 lines
+     = 15360 bytes
+CPU:    48 cycles / 2 * 24 rows * 8 lines
+     + 128 cycles / 2 * (312 - (24 rows * 8 lines))
+     = 12288 bytes
+
+MODE 4, 5:
+ULA:    40 cycles * 256 lines
+     = 10240 bytes
+CPU:   (40 cycles + 48 cycles / 2) * 256 lines
+     + 128 cycles / 2 * (312 - 256) lines
+     = 19968 bytes
+
+MODE 6:
+ULA:    40 cycles * 24 rows * 8 lines
+     = 7680 bytes
+CPU:   (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
+     + 128 cycles / 2 * (312 - (24 rows * 8 lines))
+     = 19968 bytes
+
+Here, the division of 2 for CPU accesses is performed to indicate that the CPU
+only uses every other access opportunity even in uncontended periods. See the
+2MHz RAM Access enhancement below for bandwidth calculations that consider
+this limitation removed.
 
 Video Timing
 ------------
@@ -320,6 +370,39 @@
 trivial change). Another pitfall is the complication that might be introduced
 to software writing bitmaps of character height to the screen.
 
+Enhancement: 2MHz RAM Access
+----------------------------
+
+Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
+when not competing with the ULA only accesses RAM every other 2MHz cycle (as
+if the ULA still needed to access the RAM), one useful enhancement would be a
+mechanism to let the CPU take over the ULA cycles outside the ULA's period of
+activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
+3.
+
+Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
+
+  Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
+  On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
+
+In MODE 4 to 6:
+ 
+  Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
+  On a non-display line:                 CCCCCCCC (instead of C_C_C_C_)
+
+This would improve CPU bandwidth as follows:
+
+                Standard ULA    Enhanced ULA
+MODE 0, 1, 2    9728 bytes      19456 bytes
+MODE 3          12288 bytes     24576 bytes
+MODE 4, 5       19968 bytes     29696 bytes
+MODE 6          19968 bytes     32256 bytes
+
+With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
+because all access opportunities to RAM are doubled. Meanwhile, in the other
+modes, some CPU accesses occur alongside ULA accesses and thus cannot be
+doubled, but the CPU bandwidth increase is still significant.
+
 Enhancement: Region Blanking
 ----------------------------