# HG changeset patch # User Paul Boddie # Date 1466544153 -7200 # Node ID d22e09bd1f7e424bb7f1d2410a563e694209ff45 # Parent 37c6315ecb876c0f42acaa8965e46e930ff7b45f Added notes about RAM access limitations preventing 2MHz RAM access by the CPU. diff -r 37c6315ecb87 -r d22e09bd1f7e Electron.txt --- a/Electron.txt Tue Jun 21 23:20:26 2016 +0200 +++ b/Electron.txt Tue Jun 21 23:22:33 2016 +0200 @@ -42,10 +42,12 @@ visible portion of a display line. However, even outside these periods of contention, it appears that the CPU still only accesses the RAM at 1MHz, even though the RAM can sustain 2MHz access (and indeed does when both the CPU and -ULA access it in turns). By allowing the CPU to entirely take over the RAM +ULA access it in turns). If the CPU were able to entirely take over the RAM outside display periods (just as the ULA can do) and to access it on every 2MHz cycle, performance would be significantly improved: the CPU would be able to do twice as much work in the largest-memory screen modes, for example. +Unfortunately, the RAM access mechanism, although supporting 2MHz operation, +does not do so in a way that is compatible with the CPU at 2MHz. Although RAM is accessed by the CPU at 1MHz, ROM is accessed at 2MHz. Thus, deploying software that runs from ROM can potentially provide significant diff -r 37c6315ecb87 -r d22e09bd1f7e ULA.txt --- a/ULA.txt Tue Jun 21 23:20:26 2016 +0200 +++ b/ULA.txt Tue Jun 21 23:22:33 2016 +0200 @@ -109,7 +109,10 @@ The CPU, when accessing the RAM alone, apparently does not make use of the vacated "slot" that the ULA would otherwise use (when interleaving accesses in MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when -accessing ROM (and potentially sideways RAM). +accessing ROM (and potentially sideways RAM). The principal limitation is the +amount of time needed between issuing an address and receiving an entire byte +from the RAM, which is approximately 7 cycles (at 16MHz): much longer than the +4 cycles that would be required for 2MHz operation. See: Acorn Electron Advanced User Guide See: Acorn Electron Service Manual @@ -597,6 +600,9 @@ modes, some CPU accesses occur alongside ULA accesses and thus cannot be doubled, but the CPU bandwidth increase is still significant. +Unfortunately, the mechanism for accessing the RAM is too slow to provide data +within the time constraints of 2MHz operation. + Enhancement: Region Blanking ----------------------------