1.1 --- a/ULA.txt Mon Nov 14 18:18:37 2016 +0100
1.2 +++ b/ULA.txt Fri Mar 31 22:50:55 2017 +0200
1.3 @@ -123,13 +123,29 @@
1.4 CPU Clock Notes
1.5 ---------------
1.6
1.7 +"The 6502 receives an external square-wave clock input signal on pin 37, which
1.8 +is usually labeled PHI0. [...] This clock input is processed within the 6502
1.9 +to form two clock outputs: PHI1 and PHI2 (pins 3 and 39, respectively). PHI2
1.10 +is essentially a copy of PHI0; more specifically, PHI2 is PHI0 after it's been
1.11 +through two inverters and a push-pull amplifier. The same network of
1.12 +transistors within the 6502 which generates PHI2 is also tied to PHI1, and
1.13 +generates PHI1 as the inverse of PHI0. The reason why PHI1 and PHI2 are made
1.14 +available to external devices is so that they know when they can access the
1.15 +CPU. When PHI1 is high, this means that external devices can read from the
1.16 +address bus or data bus; when PHI2 is high, this means that external devices
1.17 +can write to the data bus."
1.18 +
1.19 +See: http://lateblt.livejournal.com/88105.html
1.20 +
1.21 "The 6502 has a synchronous memory bus where the master clock is divided into
1.22 two phases (Phase 1 and Phase 2). The address is always generated during Phase
1.23 1 and all memory accesses take place during Phase 2."
1.24
1.25 -Thus, the inverse of PHI OUT provides the other phase of the clock.
1.26 +See: http://www.jmargolin.com/vgens/vgens.htm
1.27
1.28 -See: http://www.jmargolin.com/vgens/vgens.htm
1.29 +Thus, the inverse of PHI OUT provides the "other phase" of the clock. "During
1.30 +Phase 1" means when PHI0 - really PHI2 - is high and "during Phase 2" means
1.31 +when PHI1 is high.
1.32
1.33 Bandwidth Figures
1.34 -----------------