1.1 --- a/ula.py Tue Oct 30 00:04:27 2012 +0100
1.2 +++ b/ula.py Tue Oct 30 23:37:12 2012 +0100
1.3 @@ -159,7 +159,7 @@
1.4
1.5 # Internal state.
1.6
1.7 - self.cycle = 0 # counter within each 2MHz period
1.8 + self.cycle = [0]*8 # counter within each 2MHz period represented by 8 latches
1.9 self.access = 0 # counter used to determine whether a byte needs reading
1.10 self.ram_address = 0 # address given to the RAM
1.11 self.data = 0 # data read from the RAM
1.12 @@ -167,6 +167,8 @@
1.13 self.writing_pixels = 0 # whether pixel data can be written
1.14 self.buffer = [BLANK]*8 # pixel buffer for decoded RAM data
1.15
1.16 + self.cycle[7] = 1 # assert the final latch (asserting the first on update)
1.17 +
1.18 self.reset_vertical()
1.19
1.20 def set_mode(self, mode):
1.21 @@ -309,9 +311,18 @@
1.22
1.23 access_ram = not self.nmi and self.access == 0 and self.read_pixels() and not self.ssub
1.24
1.25 + # Update the state of the device.
1.26 + # NOTE: This is not meant to be "nice" Python, but instead models the
1.27 + # NOTE: propagation of state through the latches.
1.28 +
1.29 + self.cycle[0], self.cycle[1], self.cycle[2], self.cycle[3], \
1.30 + self.cycle[4], self.cycle[5], self.cycle[6], self.cycle[7] = \
1.31 + self.cycle[7], self.cycle[0], self.cycle[1], self.cycle[2], \
1.32 + self.cycle[3], self.cycle[4], self.cycle[5], self.cycle[6]
1.33 +
1.34 # Set row address (for ULA access only).
1.35
1.36 - if self.cycle == 0:
1.37 + if self.cycle[0]:
1.38
1.39 # NOTE: Propagate CPU address here.
1.40
1.41 @@ -328,7 +339,7 @@
1.42
1.43 # Latch row address, set column address (for ULA access only).
1.44
1.45 - elif self.cycle == 1:
1.46 + elif self.cycle[1]:
1.47
1.48 # NOTE: Permit CPU access here.
1.49
1.50 @@ -342,7 +353,7 @@
1.51
1.52 # Latch column address.
1.53
1.54 - elif self.cycle == 2:
1.55 + elif self.cycle[2]:
1.56
1.57 # NOTE: Permit CPU access here.
1.58
1.59 @@ -352,7 +363,7 @@
1.60 # Read 4 bits (for ULA access only).
1.61 # NOTE: Perhaps map alternate bits, not half-bytes.
1.62
1.63 - elif self.cycle == 3:
1.64 + elif self.cycle[3]:
1.65
1.66 # NOTE: Propagate CPU data here.
1.67
1.68 @@ -361,7 +372,7 @@
1.69
1.70 # Set column address (for ULA access only).
1.71
1.72 - elif self.cycle == 4:
1.73 + elif self.cycle[4]:
1.74 self.ram.column_deselect()
1.75
1.76 # NOTE: Propagate CPU address here.
1.77 @@ -371,7 +382,7 @@
1.78
1.79 # Latch column address.
1.80
1.81 - elif self.cycle == 5:
1.82 + elif self.cycle[5]:
1.83
1.84 # NOTE: Permit CPU access here.
1.85
1.86 @@ -381,7 +392,7 @@
1.87 # Read 4 bits (for ULA access only).
1.88 # NOTE: Perhaps map alternate bits, not half-bytes.
1.89
1.90 - elif self.cycle == 6:
1.91 + elif self.cycle[6]:
1.92
1.93 # NOTE: Propagate CPU data here.
1.94
1.95 @@ -396,7 +407,7 @@
1.96
1.97 # Reset addresses.
1.98
1.99 - elif self.cycle == 7:
1.100 + elif self.cycle[7]:
1.101 self.ram.column_deselect()
1.102 self.ram.row_deselect()
1.103
1.104 @@ -404,8 +415,6 @@
1.105
1.106 self.access = (self.access + 1) % self.access_frequency
1.107
1.108 - self.cycle = (self.cycle + 1) % 8
1.109 -
1.110
1.111
1.112 # Video signalling.