1.1 --- a/ULA.txt Fri Mar 06 01:13:44 2015 +0100
1.2 +++ b/ULA.txt Tue Aug 25 22:57:24 2015 +0200
1.3 @@ -839,6 +839,31 @@
1.4 as RAM-resident hardware sprites or indeed any feature demanding RAM access
1.5 concurrent with the production of the display image.
1.6
1.7 +Enhancement: Multiple CPU Stacks
1.8 +--------------------------------
1.9 +
1.10 +The 6502 maintains a stack for subroutine calls and register storage in page
1.11 +&01. Although the stack register can be manipulated using the TSX and TXS
1.12 +instructions, thereby permitting the maintenance of multiple stack regions and
1.13 +thus the potential coexistence of multiple programs each using a separate
1.14 +region, only programs that make little use of the stack (perhaps avoiding
1.15 +deeply-nested subroutine invocations and significant register storage) would
1.16 +be able to coexist without overwriting each other's stacks.
1.17 +
1.18 +One way that this issue could be alleviated would involve the provision of a
1.19 +facility to redirect accesses to page &01 to other areas of memory. The ULA
1.20 +would provide a register that defines a physical page for the use of the CPU's
1.21 +"logical" page &01, and upon any access to page &01 by the CPU, the ULA would
1.22 +change the asserted address lines to redirect the access to the appropriate
1.23 +physical region.
1.24 +
1.25 +By providing an 8-bit register, mapping to the most significant byte (MSB) of
1.26 +a 16-bit address, the ULA could then replace any MSB equal to &01 with the
1.27 +register value before the access is made. Where multiple programs coexist,
1.28 +upon switching programs, the register would be updated to point the ULA to the
1.29 +appropriate stack location, thus providing a simple memory management unit
1.30 +(MMU) capability.
1.31 +
1.32 ULA Pin Functions
1.33 -----------------
1.34