1.1 --- a/ULA.txt Tue Aug 25 22:57:24 2015 +0200
1.2 +++ b/ULA.txt Sun Sep 06 13:41:27 2015 +0200
1.3 @@ -70,10 +70,60 @@
1.4 communicate the latter behaviour. In the TM4164EC4 datasheet, it appears that
1.5 "page mode" provides the appropriate behaviour for that particular product.
1.6
1.7 +The CPU, when accessing the RAM alone, apparently does not make use of the
1.8 +vacated "slot" that the ULA would otherwise use (when interleaving accesses in
1.9 +MODE 4, 5 and 6). It only employs a full 2MHz access frequency to memory when
1.10 +accessing ROM (and potentially sideways RAM).
1.11 +
1.12 See: Acorn Electron Advanced User Guide
1.13 See: Acorn Electron Service Manual
1.14 http://acorn.chriswhy.co.uk/docs/Acorn/Manuals/Acorn_ElectronSM.pdf
1.15 See: http://mdfs.net/Docs/Comp/Electron/Techinfo.htm
1.16 +See: http://stardot.org.uk/forums/viewtopic.php?p=120438#p120438
1.17 +
1.18 +Bandwidth Figures
1.19 +-----------------
1.20 +
1.21 +Using an observation of 128 2MHz cycles per scanline, 256 active lines and 312
1.22 +total lines, with 80 cycles occurring in the active periods of display
1.23 +scanlines, the following bandwidth calculations can be performed:
1.24 +
1.25 +Total theoretical maximum:
1.26 + 128 cycles * 312 lines
1.27 + = 39936 bytes
1.28 +
1.29 +MODE 0, 1, 2:
1.30 +ULA: 80 cycles * 256 lines
1.31 + = 20480 bytes
1.32 +CPU: 48 cycles / 2 * 256 lines
1.33 + + 128 cycles / 2 * (312 - 256) lines
1.34 + = 9728 bytes
1.35 +
1.36 +MODE 3:
1.37 +ULA: 80 cycles * 24 rows * 8 lines
1.38 + = 15360 bytes
1.39 +CPU: 48 cycles / 2 * 24 rows * 8 lines
1.40 + + 128 cycles / 2 * (312 - (24 rows * 8 lines))
1.41 + = 12288 bytes
1.42 +
1.43 +MODE 4, 5:
1.44 +ULA: 40 cycles * 256 lines
1.45 + = 10240 bytes
1.46 +CPU: (40 cycles + 48 cycles / 2) * 256 lines
1.47 + + 128 cycles / 2 * (312 - 256) lines
1.48 + = 19968 bytes
1.49 +
1.50 +MODE 6:
1.51 +ULA: 40 cycles * 24 rows * 8 lines
1.52 + = 7680 bytes
1.53 +CPU: (40 cycles + 48 cycles / 2) * 24 rows * 8 lines
1.54 + + 128 cycles / 2 * (312 - (24 rows * 8 lines))
1.55 + = 19968 bytes
1.56 +
1.57 +Here, the division of 2 for CPU accesses is performed to indicate that the CPU
1.58 +only uses every other access opportunity even in uncontended periods. See the
1.59 +2MHz RAM Access enhancement below for bandwidth calculations that consider
1.60 +this limitation removed.
1.61
1.62 Video Timing
1.63 ------------
1.64 @@ -320,6 +370,39 @@
1.65 trivial change). Another pitfall is the complication that might be introduced
1.66 to software writing bitmaps of character height to the screen.
1.67
1.68 +Enhancement: 2MHz RAM Access
1.69 +----------------------------
1.70 +
1.71 +Given that the CPU and ULA both access RAM at 2MHz, but given that the CPU
1.72 +when not competing with the ULA only accesses RAM every other 2MHz cycle (as
1.73 +if the ULA still needed to access the RAM), one useful enhancement would be a
1.74 +mechanism to let the CPU take over the ULA cycles outside the ULA's period of
1.75 +activity comparable to the way the ULA takes over the CPU cycles in MODE 0 to
1.76 +3.
1.77 +
1.78 +Thus, the RAM access cycles would resemble the following in MODE 0 to 3:
1.79 +
1.80 + Upon a transition from display cycles: UUUUCCCC (instead of UUUUC_C_)
1.81 + On a non-display line: CCCCCCCC (instead of C_C_C_C_)
1.82 +
1.83 +In MODE 4 to 6:
1.84 +
1.85 + Upon a transition from display cycles: CUCUCCCC (instead of CUCUC_C_)
1.86 + On a non-display line: CCCCCCCC (instead of C_C_C_C_)
1.87 +
1.88 +This would improve CPU bandwidth as follows:
1.89 +
1.90 + Standard ULA Enhanced ULA
1.91 +MODE 0, 1, 2 9728 bytes 19456 bytes
1.92 +MODE 3 12288 bytes 24576 bytes
1.93 +MODE 4, 5 19968 bytes 29696 bytes
1.94 +MODE 6 19968 bytes 32256 bytes
1.95 +
1.96 +With such an enhancement, MODE 0 to 3 experience a doubling of CPU bandwidth
1.97 +because all access opportunities to RAM are doubled. Meanwhile, in the other
1.98 +modes, some CPU accesses occur alongside ULA accesses and thus cannot be
1.99 +doubled, but the CPU bandwidth increase is still significant.
1.100 +
1.101 Enhancement: Region Blanking
1.102 ----------------------------
1.103