paul@35 | 1 | #ifndef __VGA_H__ |
paul@35 | 2 | #define __VGA_H__ |
paul@35 | 3 | |
paul@38 | 4 | #define LINE_LENGTH 160 /* pixels */ |
paul@38 | 5 | #define LINE_COUNT 256 /* distinct display lines */ |
paul@35 | 6 | |
paul@61 | 7 | #define HFREQ_LIMIT 1286 /* 48MHz cycles */ |
paul@61 | 8 | #define HSYNC_START 920 /* 48MHz cycles */ |
paul@61 | 9 | #define HSYNC_LIMIT 128 /* 48MHz cycles */ |
paul@35 | 10 | #define HSYNC_END (HSYNC_START + HSYNC_LIMIT) |
paul@35 | 11 | |
paul@38 | 12 | #define VISIBLE_START 70 /* horizontal lines, back porch end */ |
paul@35 | 13 | #define VFP_START (VISIBLE_START + 2 * LINE_COUNT) |
paul@38 | 14 | #define VSYNC_START 620 /* horizontal lines, front porch end */ |
paul@38 | 15 | #define VSYNC_END 622 /* horizontal lines, back porch start */ |
paul@35 | 16 | |
paul@38 | 17 | #define SCREEN_BASE 256 |
paul@35 | 18 | #define SCREEN_SIZE (40 * 1024) |
paul@41 | 19 | #define SCREEN_LIMIT (SCREEN_BASE + SCREEN_SIZE) |
paul@35 | 20 | |
paul@38 | 21 | #define SCREEN_BASE_KSEG0 (KSEG0_BASE + SCREEN_BASE) |
paul@41 | 22 | #define SCREEN_LIMIT_KSEG0 (KSEG0_BASE + SCREEN_LIMIT) |
paul@38 | 23 | |
paul@38 | 24 | #define IRQ_STACK_LIMIT SCREEN_BASE_KSEG0 |
paul@38 | 25 | #define IRQ_STACK_TOP (IRQ_STACK_LIMIT - 56) |
paul@38 | 26 | |
paul@35 | 27 | #endif /* __VGA_H__ */ |